TABLE 2. Power Down Configuration

CE Pin

RF_EN

IF_EN

RF Circuitry

IF Circuitry

0

X

X

OFF

OFF

1

0

0

OFF

OFF

1

0

1

OFF

ON

1

1

0

ON

OFF

11

1

ON

ON

X = Don’t care.

LOCK DETECT

The LD output can be used to indicate the lock status of the

RF PLL. Bit 21 in Register R0 determines the signal that

appears on the LD pin. When the RF PLL is not locked, the

LD pin remains LOW. After obtaining phase lock, the LD pin

will have a logical HIGH level. The output can also be

programmed to be ground at all times.

TABLE 3. Lock Detect Modes

LD Bit

Mode

0

Disable (GND)

1

Enable

TABLE 4. Lock Detect Logic

RF PLL Section

LD Output

Locked

HIGH

Not Locked

LOW

four or more consecutive cycles.

Note 11: Phase Error is measured on leading edge. Only errors greater than

20068005

FIGURE 1. Lock Detect Timing Diagram Waveform (Notes 9, 10, 11, 12, 13)

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