Functional Description

The simplified block diagram below shows the 19-bit data register the 14-bit R Counter and the S Latch and the 18-bit

N Counter (intermediate latches are not shown) The data stream is clocked (on the rising edge) into the DATA input MSB first

If the Control Bit (last bit input) is HIGH the DATA is transferred into the R Counter (programmable reference divider) and the

S Latch (prescaler select LMX2315 and LMX2320 6465 or 128129 LMX2325 3233 or 6465) If the Control Bit (LSB) is

LOW the DATA is transferred into the N Counter (programmable divider)

TLW12339 – 18

PROGRAMMABLE REFERENCE DIVIDER (R COUNTER) AND PRESCALER SELECT (S LATCH)

If the Control Bit (last bit shifted into the Data Register) is HIGH data is transferred from the 19-bit shift register into a 14-bit

latch (which sets the 14-bit R Counter) and the 1-bit S Latch (S15 which sets the prescaler 6465 or 128129 for the

LMX231520 or 3233 or 6465 for the LMX2325) Serial data format is shown below

TLW12339 – 6

14-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO

(R COUNTER)

Divide

14

S

13

S

12

S

11

S

10

SS

9

S

8

S

7

S

6

S

5

S

4

S

3

S

2

S

1

Ratio

R

3

0

0000

0 0 0 000011

4

0

0000

0 0 0 000100









16383

1

1111

1 1 1 111111

Notes

Divide ratios less than 3 are prohibited

Divide ratio 3 to 16383

S1 to S14 These bits select the divide ratio of the programmable

reference divider

C Control bit (set to HIGH level to load R counter and S Latch)

Data is shifted in MSB first

Prescaler Select

15

S

LMX231520

LMX2325

128129

6465

0

6465

3233

1

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