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LMX2346 Datasheet(PDF) 21 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. LMX2346
Description  PLLatinum™ Frequency Synthesizer for RF Personal Communications
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

LMX2346 Datasheet(HTML) 21 Page - National Semiconductor (TI)

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1.0 Functional Description (Continued)
The programmable register set is accessed via the
Microwire serial interface. The interface is comprised of
three signal pins: CLOCK, DATA, and LE (Latch Enable).
Serial data is clocked in from DATA on the rising edge of
CLOCK, into an 18-bit shift register. The serial data is
clocked in MSB first. The last bit of data decodes the internal
register address. On the rising edge of LE, the data stored in
the shift register is loaded into one of the two appropriate
latches based on the address bit. A complete programming
description is provided in Section 2.0.
The LMX2346/7 LD pin is a multi-function output that can be
configured as a digital lock detect, an analog lock detect, as
well as monitor the output of the reference divider, or feed-
back divider circuits. The LD_OUT control word is used to
select the desired output function. When the PLL is in power-
down mode, the LD output is always set to a high imped-
ance. A complete programming description of the multi-
function output is provided in Section 2.2.4.
1.8.1 Analog Lock Detect
When LD_OUT = 1, an analog lock detect status generated
from the phase detector is available on the LD output pin.
The lock detect output goes to high impedance when the
charge pump is inactive. It goes low when the charge pump
is active during a comparison cycle. The analog lock detect
signal output is an open drain configuration.
1.8.2 Digital Lock Detect
When LD_OUT = 0, a digital lock detect status is available
on the LD output pin. The digital lock detect filter compares
the phase difference of the inputs from the phase detector to
a RC generated delay of approximately 15 ns. To enter the
locked state (LD = High), the phase error must be less than
the 15 ns RC delay for 5 consecutive reference cycles. Once
in lock, the RC delay is changed to approximately 30 ns. To
exit the locked state, the phase error must be greater than
the 30 ns RC delay. A flow chart of the digital lock detect filter

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