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MC68302FC20 Datasheet(PDF) 17 Page - Motorola, Inc

Part No. MC68302FC20
Description  Integrated Multiprotocol Processor User’s Manual
Download  480 Pages
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Maker  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com
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MC68302FC20 Datasheet(HTML) 17 Page - Motorola, Inc

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MOTOROLA
MC68302 USER’S MANUAL
xvii
LIST OF FIGURES
Figure
Title
Page
Number
Number
Section 1
General Description
Figure 1-1.
MC68302 Block Diagram ........................................................................... 1-2
Figure 1-2.
General-Purpose Microprocessor System Design ..................................... 1-4
Figure 1-3.
MC68302 System Design........................................................................... 1-5
Figure 1-4.
NMSI Communications-Oriented Board Design......................................... 1-7
Figure 1-5.
Basic Rate IDL Voice/Data Terminal in ISDN ............................................ 1-8
Section 2
MC68000/MC68008 Core
Figure 2-1.
M68000 Programming Model ..................................................................... 2-2
Figure 2-2.
M68000 Status Register............................................................................. 2-3
Figure 2-3.
M68000 Bus/Address Error Exception Stack Frame................................ 2-10
Figure 2-4.
M68000 Short-Form Exception Stack Frame ........................................... 2-10
Figure 2-5.
MC68302 IMP Configuration Control ....................................................... 2-12
Section 3
System Integration Block (SIB)
Figure 3-1.
IDMA Controller Block Diagram ................................................................. 3-3
Figure 3-2.
Interrupt Controller Block Diagram ........................................................... 3-16
Figure 3-3.
Interrupt Request Logic Diagram for SCCs.............................................. 3-21
Figure 3-4.
SCC1 Vector Calculation Example........................................................... 3-23
Figure 3-5.
Parallel I/O Block Diagram for PA0 .......................................................... 3-30
Figure 3-6.
Parallel I/O Port Registers........................................................................ 3-33
Figure 3-7.
RAM Block Diagram ................................................................................. 3-35
Figure 3-8.
Timer Block Diagram................................................................................ 3-36
Figure 3-9.
Chip-Select Block Diagram ...................................................................... 3-44
Figure 3-10. Using an External Crystal......................................................................... 3-49
Figure 3-11. System Control Register .......................................................................... 3-50
Figure 3-12. IMP Bus Arbiter ........................................................................................ 3-57
Figure 3-13. DRAM Control Block Diagram.................................................................. 3-67
Section 4
Communications Processor (CP)
Figure 4-1.
Simplified CP Architecture.......................................................................... 4-2
Figure 4-2.
Three Serial Data Flow Paths .................................................................... 4-4
Figure 4-3.
NMSI Physical Interface ............................................................................. 4-8
Figure 4-4.
Multiplexed Mode on SCC1 Opens Additional Configuration
Possibilities................................................................................................. 4-9


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