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MC68302FC20 Datasheet(PDF) 16 Page - Motorola, Inc

Part No. MC68302FC20
Description  Integrated Multiprotocol Processor User’s Manual
Download  480 Pages
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Maker  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com
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MC68302FC20 Datasheet(HTML) 16 Page - Motorola, Inc

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Table of Contents
Paragraph
Title
Page
Number
Number
xvi
MC68302 USER’S MANUAL
MOTOROLA
E.2.1.4.2
Receive Buffer Data Length.................................................................. E-27
E.2.1.4.3
Receive Buffer Pointer. ......................................................................... E-27
E.2.1.5
Transmit Buffer Descriptors. ................................................................. E-27
E.2.1.5.1
Transmit BD Control/Status Word......................................................... E-27
E.2.1.5.2
Transmit Buffer Data Length................................................................. E-28
E.2.2
Programming the SCC for UART.......................................................... E-28
E.2.2.1
Initialization ........................................................................................... E-29
E.2.2.2
General and UART Protocol-Specific RAM Initialization....................... E-29
E.2.2.3
SCC Initialization................................................................................... E-29
E.2.2.4
SCC Operation...................................................................................... E-29
E.2.2.5
SCC Interrupt Handling......................................................................... E-30
E.3
Transparent Programming Reference Section ..................................... E-30
E.3.1
Transparent Programming Model ......................................................... E-30
E.3.1.1
Communications Processor (CP) Registers ......................................... E-32
E.3.1.1.1
Command Register (CR). ..................................................................... E-32
E.3.1.1.2
Serial Interface Mode Register (SIMODE)............................................ E-33
E.3.1.1.3
Serial Interface Mask Register (SIMASK)............................................. E-34
E.3.1.2
PER SCC Registers.............................................................................. E-35
E.3.1.2.1
Serial Configuration Register (SCON) .................................................. E-35
E.3.1.2.2
SCC Mode Register (SCM)................................................................... E-35
E.3.1.2.3
SCC Data Synchronization Register (DSR).......................................... E-36
E.3.1.2.4
Transparent Event Register (SCCE)..................................................... E-36
E.3.1.2.5
Transparent Mask Register (SCCM)..................................................... E-37
E.3.1.2.6
Transparent Status Register (SCCS).................................................... E-38
E.3.1.3
General and Transparent Protocol-Specific Parameter RAM ............... E-38
E.3.1.3.1
RFCR/TFCR—Rx Function Code/Tx Function Code............................ E-38
E.3.1.3.2
MRBLR—Maximum Rx Buffer Length .................................................. E-38
E.3.1.4
Receive Buffer Descriptors. .................................................................. E-38
E.3.1.4.1
Receive BD Control/Status Word.......................................................... E-38
E.3.1.4.2
Receive Buffer Data Length.................................................................. E-39
E.3.1.4.3
Receive Buffer Pointer .......................................................................... E-39
E.3.1.5
Transmit Buffer Descriptors. ................................................................. E-39
E.3.1.5.1
Transmit BD Control/Status Word......................................................... E-39
E.3.1.5.2
Transmit Buffer Data Length................................................................. E-40
E.3.1.5.3
Transmit Buffer Pointer ......................................................................... E-40
E.3.2
Programming the SCC for Transparent ................................................ E-40
E.3.2.1
CP Initialization ..................................................................................... E-40
E.3.2.2
General and Transparent Protocol-Specific RAM Initialization ............. E-41
E.3.2.3
SCC Initialization................................................................................... E-41
E.3.2.4
SCC Operation...................................................................................... E-41
E.3.2.5
SCC Interrupt Handling......................................................................... E-41
Appendix F
Design Checklist


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