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MC68302FC20 Datasheet(PDF) 15 Page - Motorola, Inc

Part No. MC68302FC20
Description  Integrated Multiprotocol Processor User’s Manual
Download  480 Pages
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Maker  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com
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MC68302FC20 Datasheet(HTML) 15 Page - Motorola, Inc

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Table of Contents
Paragraph
Title
Page
Number
Number
MOTOROLA
MC68302 USER’S MANUAL
xv
E.1.1.3.6
ABTSC—Abort Sequence Counter. ...................................................... E-10
E.1.1.3.7
NMARC—Nonmatching Address Received Counter. ........................... E-10
E.1.1.3.8
RETRC—Frame Retransmission Counter. ........................................... E-10
E.1.1.3.9
MFLR—Maximum Frame Length Register............................................ E-10
E.1.1.3.10
HMASK—HDLC Frame Address Mask ................................................. E-10
E.1.1.3.11
HADDR1, HADDR2, HADDR3, and HADDR4-HDLC Frame Address.. E-10
E.1.1.4
Receive Buffer Descriptors.................................................................... E-10
E.1.1.4.1
Receive BD Control/Status Word. ......................................................... E-11
E.1.1.4.2
Receive Buffer Data Length. ................................................................. E-12
E.1.1.4.3
Receive Buffer Pointer. ......................................................................... E-12
E.1.1.5
Transmit Buffer Descriptors................................................................... E-12
E.1.1.5.1
Transmit BD Control/Status Word. ........................................................ E-12
E.1.1.5.2
Transmit Buffer Data Length. ................................................................ E-13
E.1.1.5.3
Transmit Buffer Pointer. ........................................................................ E-13
E.1.2
Programming the SCC for HDLC .......................................................... E-13
E.1.2.1
CP Initialization...................................................................................... E-13
E.1.2.2
General and HDLC Protocol-Specific RAM Initialization ....................... E-13
E.1.2.3
SCC Initialization ................................................................................... E-14
E.1.2.4
SCC Operation ...................................................................................... E-14
E.1.2.5
SCC Interrupt Handling ......................................................................... E-14
E.2
UART Programming Reference Section ............................................... E-15
E.2.1
UART Programming Model ................................................................... E-15
E.2.1.1
Communications Processor (CP) Registers.......................................... E-17
E.2.1.1.1
Command Register (CR)....................................................................... E-17
E.2.1.1.2
Serial lnterface Mode Register (SlMODE)............................................. E-18
E.2.1.1.3
Serial Interface Mask Register (SIMASK). ............................................ E-19
E.2.1.2
Per SCC Registers. ............................................................................... E-19
E.2.1.2.1
Serial Configuration Register (SCON)................................................... E-19
E.2.1.2.2
SCC Mode Register (SCM). .................................................................. E-20
E.2.1.2.3
SCC Data Synchronization Register (DSR). ......................................... E-22
E.2.1.2.4
UART Event Register (SCCE)............................................................... E-22
E.2.1.2.5
UART Mask Register (SCCM)............................................................... E-23
E.2.1.2.6
UART Status Register (SCCS).............................................................. E-23
E.2.1.3
General and UART Protocol-specific Parameter RAM.......................... E-23
E.2.1.3.1
RFCR/TFCR—Rx Function Code/Tx Function Code. ........................... E-24
E.2.1.3.2
MRBLR—Maximum Rx Buffer Length................................................... E-24
E.2.1.3.3
MAX_IDL—Maximum IDLE Characters. ............................................... E-24
E.2.1.3.4
BRKCR—Break Count Register............................................................ E-24
E.2.1.3.5
PAREC—Receive Parity Error Counter. ............................................... E-24
E.2.1.3.6
FRMEC—Receive Framing Error Counter. ........................................... E-24
E.2.1.3.7
NOSEC—Receive Noise Counter. ........................................................ E-24
E.2.1.3.8
BRKEC—Receive Break Condition Counter. ........................................ E-24
E.2.1.3.9
UADDR1 and UADDR2......................................................................... E-24
E.2.1.4
Receive Buffer Descriptors.................................................................... E-25
E.2.1.4.1
Receive BD Control/Status Word. ......................................................... E-26


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