Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

MC68302FC20 Datasheet(PDF) 98 Page - Motorola, Inc

Part No. MC68302FC20
Description  Integrated Multiprotocol Processor User’s Manual
Download  480 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com
Logo 

MC68302FC20 Datasheet(HTML) 98 Page - Motorola, Inc

Zoom Inzoom in Zoom Outzoom out
 98 / 480 page
background image
System Integration Block (SIB)
3-48
MC68302 USER’S MANUAL
MOTOROLA
NOTE
Do not assert DTACK externally when it is programmed to be
generated internally.
Bits 12–2—Base Address Mask
These bits are used to set the block size of a particular chip-select line. The address com-
pare logic uses only the address bits that are not masked (i.e., mask bit set to one) to de-
tect an address match within its block size.
0 = The address bit in the corresponding BR is masked; the address compare logic
does not use this address bit. The corresponding external address line value is a
don't care in the comparison.
1 = The address bit in the corresponding BR is not masked; the address compare logic
uses this address bit.
For example, for a 64K-byte block, this field should be M13, M14, M15 = 0 with the rest of
the base address mask bits (M23–M16) equal to one.
After system reset, the bits of the base address mask field default to ones (selecting the
smallest block size of 8K) to allow CS0 to select the ROM device containing the reset vector.
MRW—Mask Read/Write
0 = The RW bit in the BR is masked. The chip select is asserted for both read and write
operations.
1 = The RW bit in the BR is not masked. The chip select is asserted for read-only or
write-only operations as programmed by the corresponding RW bit in BR3–BR0.
After system reset, this bit defaults to zero.
CFC—Compare Function Code
0 = The FC bits in the BR are ignored. The chip select is asserted without comparing
the FC bits. If the application requires the user to recognize several address spac-
es (e.g., user space without distinguishing between data and program space), FC
bits must be decoded externally.
1 = The FC bits on the BR are compared. The address space compare logic uses the
FC bits to assert the CS line.
After system reset, this bit defaults to one.
NOTE
Even when CFC = 0, if the function code lines are internally or
externally generated as “111”, the chip select will not be assert-
ed.
3.6.3 Chip Select Example
Set up chip select 2 to assert for a 1 Megabyte block of external RAM beginning at $200000
with 1 wait state. Note that the address must be on a block boundary (i.e. the starting ad-
dress of a 1 Megabyte block could not be $210000).


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61  62  63  64  65  66  67  68  69  70  71  72  73  74  75  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90  91  92  93  94  95  96  97  98  99  100   ...More


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn