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MC68302FC20 Datasheet(PDF) 97 Page - Motorola, Inc

Part No. MC68302FC20
Description  Integrated Multiprotocol Processor User’s Manual
Download  480 Pages
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Maker  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com
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MC68302FC20 Datasheet(HTML) 97 Page - Motorola, Inc

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System Integration Block (SIB)
MOTOROLA
MC68302 USER’S MANUAL
3-47
EN—Enable
0 = The chip-select line is disabled.
1 = The chip-select line is enabled.
After system reset, only CS0 is enabled; CS3–CS1 are disabled. In disable CPU mode,
CS3–CS0 are disabled at system reset. The chip select does not require disabling before
changing its parameters.
3.6.2.2 Option Registers (OR3–OR0)
These four 16-bit registers consist of a base address mask field, a read/write mask bit, a
compare function code bit, and a DTACK generation field.
Bits 15–12—DTACK Field
These bits are used to determine whether DTACK is generated internally with a program-
mable number of wait states or externally by the peripheral. With internal DTACK gener-
ation, zero to six wait states can be automatically inserted before the DTACK pin is
asserted as an output (see Port A Control Register (PACNT)).
When all the bits in this field are set to one, DTACK must be generated externally, and the
IMP or external bus master waits for DTACK (input) to terminate its bus cycle. After system
reset, the bits of the DTACK field default to six wait states.
The DTACK generator uses the IMP internal clock to generate the programmable number
of wait states. For asynchronous external bus masters, the programmable number of wait
states is counted directly from the internal clock. When no wait state is programmed
(DTACK = 000), the DTACK generator will generate DTACK asynchronously.
The CS lines are asserted slightly earlier for internal IMP master memory cycles than for an
external master using the CS lines. Set external master wait state (EMWS) in the SCR
whenever these timing differences require an extra memory wait state for external masters.
15
13
12
210
DTACK
BASE ADDRESS MASK (M23–M13)
MRW
CFC
Table 3-8. DTACK Field Encoding
Bits
Description
15
14
13
0
0
0
No Wait State
0
0
1
1 Wait State
0
1
0
2 Wait States
0
1
1
3 Wait States
1
0
0
4 Wait States
1
0
1
5 Wait States
1
1
0
6 Wait States
1
1
1
External DTACK


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