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MC68302FC20 Datasheet(PDF) 93 Page - Motorola, Inc

Part No. MC68302FC20
Description  Integrated Multiprotocol Processor User’s Manual
Download  480 Pages
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Maker  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com
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MC68302FC20 Datasheet(HTML) 93 Page - Motorola, Inc

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System Integration Block (SIB)
MOTOROLA
MC68302 USER’S MANUAL
3-43
DTACK generation occurs under the same constraints as the chip-select signal—if the chip-
select signal does not activate, then neither will the DTACK signal.
Chip select 0 has the special property of being enabled upon system reset to the address
range from 0 to 8K bytes. This property allows chip select 0 to function as the “boot ROM”
select on system start-up. DTACK is initially enabled for six wait states on this chip select.
External masters may use the chip-select logic on the IMP during an external master access
to external memory/peripherals. In this case, the external master chip-select timing diagram
(see Figure 6-15) must be used. Since the chip-select logic is slightly slower when using ex-
ternal masters, an optional provision can be made to add an additional wait state to an ex-
ternal access by an external master. See the EMWS bit in the SCR for more details (3.8.3
System Control Bits).
A priority structure exists within the chip-select block. For a given address, the priority is as
follows:
1. Access to any IMP internal address (BAR, dual-port RAM, etc.)
No chip select asserted.
2. Chip Select 0
3. Chip Select 1
4. Chip Select 2
5. Chip Select 3


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