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MC68302FC20 Datasheet(PDF) 89 Page - Motorola, Inc

Part No. MC68302FC20
Description  Integrated Multiprotocol Processor User’s Manual
Download  480 Pages
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Maker  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com
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MC68302FC20 Datasheet(HTML) 89 Page - Motorola, Inc

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System Integration Block (SIB)
MOTOROLA
MC68302 USER’S MANUAL
3-39
When working in the MC68008 mode (BUSW is low), writing the high byte of TRR1 and
TRR2 will disable the timer's compare logic until the low byte is written.
TRR1 and TRR2 are set to all ones by reset. The reference value is not “reached” until TCN
increments to equal TRR.
3.5.2.3 Timer Capture Registers (TCR1, TCR2)
Each TCR is a 16-bit register used to latch the value of the counter during a capture opera-
tion when an edge occurs on the respective TIN1 or TIN2 pin. TCR1 and TCR2 appear as
memory-mapped read-only registers to the user.
When working in the MC68008 mode (BUSW is low), reading the high byte of TCR1 and
TCR2 will disable the timer's capture logic until the low byte is read.
TCR1 and TCR2 are cleared at reset.
3.5.2.4 Timer Counter (TCN1, TCN2)
TCN1 and TCN2 are 16-bit up-counters. Each is memory-mapped and can be read and writ-
ten by the user. A read cycle to TCN1 and TCN2 yields the current value of the timer and
does not affect the counting operation.
When working in the MC68008 mode (BUSW is low), reading the high byte of TCN1 and
TCN2 will latch the low byte into a temporary register; a subsequent read cycle on the low
byte yields the value of the temporary register.
A write cycle to TCN1 and TCN2 causes both the counter register and the corresponding
prescaler to be reset to zero. In MC68008 mode (BUSW is low), a write cycle to either the
high or low byte of the TCN will reset the counter register and the corresponding prescaler
to zero.
3.5.2.5 Timer Event Registers (TER1, TER2)
Each TER is an 8-bit register used to report events recognized by any of the timers. On rec-
ognition of an event, the timer will set the appropriate bit in the TER, regardless of the cor-
responding interrupt enable bits (ORI and CE) in the TMR. TER1 and TER2, which appear
to the user as memory-mapped registers, may be read at any time.
A bit is cleared by writing a one to that bit (writing a zero does not affect a bit's value). More
than one bit may be cleared at a time. Both bits must be cleared before the timer will negate
the INRQ to the interrupt controller. This register is cleared at reset.
CAP—Capture Event
The counter value has been latched into the TCR. The CE bits in the TMR are used to
enable the interrupt request caused by this event.
7
210
RESERVED
REF
CAP


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