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MC68302FC20 Datasheet(PDF) 87 Page - Motorola, Inc

Part No. MC68302FC20
Description  Integrated Multiprotocol Processor User’s Manual
Download  480 Pages
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Maker  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com
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MC68302FC20 Datasheet(HTML) 87 Page - Motorola, Inc

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System Integration Block (SIB)
MOTOROLA
MC68302 USER’S MANUAL
3-37
The watchdog timer has the following features:
• A 16-Bit Counter and Reference Register
• Maximum Period of 16.78 Seconds (at 16 MHz)
• 0.5 ms Resolution (at 16 MHz)
• Output Signal (WDOG)
• Interrupt Capability
3.5.2 General Purpose Timer Units
The clock input to the prescaler may be selected from the main clock (divided by 1 or by 16)
or from the corresponding timer input (TIN) pin. TIN is internally synchronized to the internal
clock. The clock input source is selected by the ICLK bits of the corresponding TMR. The
prescaler is programmed to divide the clock input by values from 1 to 256. The output of the
prescaler is used as an input to the 16-bit counter.
The resolution of the timer is one clock cycle (60 ns at 16.67 MHz). The maximum period
(when the reference value is all ones) is 268,435,456 cycles (16.78 seconds at 16.00 MHz).
Each timer may be configured to count until a reference is reached and then either resets to
zero on the next clock or continues to run. The free run/restart (FRR) bit of the correspond-
ing TMR selects each mode. Upon reaching the reference value, the corresponding TER bit
is set, and an interrupt is issued if the output reference interrupt enable (ORI) bit in TMR is
set.
Each timer may output a signal on the timer output (TOUT1 or TOUT2) pin when the refer-
ence value is reached, as selected by the output mode (OM) bit of the corresponding TMR.
This signal can be an active-low pulse for one clock cycle or a toggle of the current output.
The output can also be used as an input to the other timer, resulting in a 32-bit timer.
Each timer has a 16-bit TCR, which is used to latch the value of the counter when a defined
transition (of TIN1 or TIN2) is sensed by the corresponding input capture edge detector. The
type of transition triggering the capture is selected by the capture edge and enable interrupt
(CE) bits in the corresponding TMR. Upon a capture or reference event, the corresponding
TER bit is set, and a maskable interrupt is issued.
The timer registers may be modified at any time by the user.
3.5.2.1 Timer Mode Register (TMR1, TMR2)
TMR1 and TMR2 are identical 16-bit registers. TMR1 and TMR2, which are memory-
mapped read-write registers to the user, are cleared by reset.
15
876543210
PRESCALER VALUE (PS)
CE
OM
ORI
FRR
ICLK
RST


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