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MC68302FC20 Datasheet(PDF) 84 Page - Motorola, Inc

Part No. MC68302FC20
Description  Integrated Multiprotocol Processor User’s Manual
Download  480 Pages
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Maker  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com
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MC68302FC20 Datasheet(HTML) 84 Page - Motorola, Inc

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System Integration Block (SIB)
3-34
MC68302 USER’S MANUAL
MOTOROLA
nously with no wait states. The external master requests the M68000 bus using the BR pin
and is granted bus ownership. The external master must then access the RAM synchro-
nously with respect to the IMP system clock with zero or one wait state, or asynchronously
as determined by the EMWS and SAM bits in the system control register. Except for several
locations initialized by the CP, the dual-port RAM is undefined at power-on reset but is not
modified by successive resets. The RAM is divided into two parts: parameter RAM and sys-
tem RAM.
The 576-byte parameter RAM area includes pointers, counters, and registers used with the
serial ports. This area is accessed by the CP during communications processing. Any indi-
vidual locations not required in a given application may be used as general-purpose RAM.
The 576-byte system RAM is a general-purpose RAM, which may be used as M68000 data
and/or program RAM or CP microcode RAM. As data RAM, it can include serial port data
buffers or can be used for other purposes such as a no-wait-state cache for the M68000
core. As CP microcode RAM, it is used exclusively to store microcode for the CP main con-
troller, allowing the development of special protocols or protocol enhancements, under spe-
cial arrangement with Motorola. Appendix C discusses available offerings.
The RAM block diagram is shown in Figure 3-7. The M68000 core, the IDMA, and the ex-
ternal master access the RAM through the IMP bus interface unit (BIU) using the M68000
bus. When an access is made, the BIU generates a wait signal to the CP main controller to
prevent simultaneous access of the RAM. The CP main controller waits for one cycle to al-
low the RAM to service the M68000 bus cycle and then regenerates its RAM cycle. This
mechanism allows the RAM to be accessed synchronously by the M68000 core, IDMA, or
external master without wait states. Thus, during the four-clock M68000 memory cycle,
three internal accesses by the CP main controller may occur. The BIU also provides the
DTACK signal output when the RAM and on-chip registers are accessed by any M68000
bus master.


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