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MC68302FC20 Datasheet(PDF) 79 Page - Motorola, Inc |
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MC68302FC20 Datasheet(HTML) 79 Page - Motorola, Inc |
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79 / 480 page 
System Integration Block (SIB) MOTOROLA MC68302 USER’S MANUAL 3-29 2. Immediately read the SCC1 event (SCCE1) register into a temporary location. 3. Decide which events in the SCCE1 will be handled in this handler and clear those bits in the SCCE1 as soon as possible. (Handle events in the SCC1 Rx or Tx BD tables.) At the end: 4. Clear the SCC1 bit in the ISR. 5. Execute RTE instruction. If any unmasked bits in SCCE1 remain at this time (either uncleared by the software or set by the IMP during the execution of this handler), this interrupt source will be made pending again immediately following the RTE instruction. In example 1, the hardware clears the TIMER3 bit in the IPR during the interrupt acknowl- edge cycle. This is an example of a handler for an interrupt source without multiple events. In example 2, the IPR bit remains set as long as one or more unmasked event bits remain the in the SCCE1 register. This is an example of a handler for an interrupt source with mul- tiple events. Note that, in both cases, it is not necessary to clear the IPR bit; however, in both cases, it is necessary to clear the ISR bit to allow future interrupts from this source. 3.3 PARALLEL I/O PORTS The IMP supports two general-purpose I/O ports, port A and port B, whose pins can be gen- eral-purpose I/O pins or dedicated peripheral interface pins. Some port B pins are always maintained as four general-purpose I/O pins, each with interrupt capability. 3.3.1 Port A Each of the 16 port A pins are independently configured as a general-purpose I/O pin if the corresponding port A control register (PACNT) bit is cleared. Port A pins are configured as dedicated on-chip peripheral pins if the corresponding PACNT bit is set. An example block diagram of PA0 is given in Figure 3-5 |
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