Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

MC68302FC20 Datasheet(PDF) 79 Page - Motorola, Inc

Part No. MC68302FC20
Description  Integrated Multiprotocol Processor User’s Manual
Download  480 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com
Logo 

MC68302FC20 Datasheet(HTML) 79 Page - Motorola, Inc

Zoom Inzoom in Zoom Outzoom out
 79 / 480 page
background image
System Integration Block (SIB)
MOTOROLA
MC68302 USER’S MANUAL
3-29
2. Immediately read the SCC1 event (SCCE1) register into a temporary location.
3. Decide which events in the SCCE1 will be handled in this handler and clear those bits
in the SCCE1 as soon as possible.
(Handle events in the SCC1 Rx or Tx BD tables.)
At the end:
4. Clear the SCC1 bit in the ISR.
5. Execute RTE instruction. If any unmasked bits in SCCE1 remain at this time (either
uncleared by the software or set by the IMP during the execution of this handler), this
interrupt source will be made pending again immediately following the RTE instruction.
In example 1, the hardware clears the TIMER3 bit in the IPR during the interrupt acknowl-
edge cycle. This is an example of a handler for an interrupt source without multiple events.
In example 2, the IPR bit remains set as long as one or more unmasked event bits remain
the in the SCCE1 register. This is an example of a handler for an interrupt source with mul-
tiple events.
Note that, in both cases, it is not necessary to clear the IPR bit; however, in both cases, it is
necessary to clear the ISR bit to allow future interrupts from this source.
3.3 PARALLEL I/O PORTS
The IMP supports two general-purpose I/O ports, port A and port B, whose pins can be gen-
eral-purpose I/O pins or dedicated peripheral interface pins. Some port B pins are always
maintained as four general-purpose I/O pins, each with interrupt capability.
3.3.1 Port A
Each of the 16 port A pins are independently configured as a general-purpose I/O pin if the
corresponding port A control register (PACNT) bit is cleared. Port A pins are configured as
dedicated on-chip peripheral pins if the corresponding PACNT bit is set. An example block
diagram of PA0 is given in Figure 3-5


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61  62  63  64  65  66  67  68  69  70  71  72  73  74  75  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90  91  92  93  94  95  96  97  98  99  100   ...More


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn