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MC68302FC20 Datasheet(PDF) 78 Page - Motorola, Inc

Part No. MC68302FC20
Description  Integrated Multiprotocol Processor User’s Manual
Download  480 Pages
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Maker  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com
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MC68302FC20 Datasheet(HTML) 78 Page - Motorola, Inc

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System Integration Block (SIB)
3-28
MC68302 USER’S MANUAL
MOTOROLA
3.2.5.4 Interrupt In-Service Register (ISR).
Each bit in the 16-bit ISR corresponds to an INRQ interrupt source. In a vectored interrupt
environment, the interrupt controller sets the ISR bit when the vector number corresponding
to the INRQ interrupt source is passed to the core during an interrupt acknowledge cycle.
The user's interrupt service routine should clear this bit during the servicing of the interrupt.
(If an event register exists for this peripheral, its bits should also be cleared by the user pro-
gram.) To clear a bit in the ISR, the user writes a one to that bit. The user can only clear bits
in this register, and bits that are written with zeros will not be affected. The ISR is cleared at
reset.
This register may be read by the user to determine which INRQ interrupts are currently being
processed. More than one bit in the ISR may be a one if the capability is used to allow higher
priority level 4 interrupts to interrupt lower priority level 4 interrupts. See 3.2.2.3 Nested In-
terrupts for more details.
The user can control the extent to which level 4 interrupts may interrupt other level 4 inter-
rupts by selectively clearing the ISR. A new INRQ interrupt will be processed if it has a higher
priority than the highest priority INRQ interrupt having its ISR bit set. Thus, if an INRQ inter-
rupt routine lowers the 3-bit mask in the M68000 core to level 3 and also clears its ISR bit
at the beginning of the interrupt routine, then a lower priority INRQ interrupt can interrupt it
as long as the lower priority is higher than any other ISR bits that are set.
If the INRQ error vector is taken, no bit in the ISR is set. Bit 0 of the ISR is always zero.
3.2.6 Interrupt Handler Examples
The following examples illustrate proper interrupt handling on the IMP. Nesting of level 4 in-
terrupts (a technique described earlier) is not implemented in the following examples.
Example 1—Timer 3 (Software Watchdog Timer) Interrupt Handler
1. Vector to interrupt handler.
2. (Handle Event)
3. Clear the TIMER3 bit in the ISR.
4. Execute RTE instruction.
Example 2— SCC1 Interrupt Handler
1. Vector to interrupt handler.
15
14
13
12
11
10
9
8
PB11
PB10
SCC1
SDMA
IDMA
SCC2
TIMER1
SCC3
76543210
PB9
TIMER2
SCP
TIMER3
SMC1
SMC2
PB8
0


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