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MC68302FC20 Datasheet(PDF) 69 Page - Motorola, Inc

Part No. MC68302FC20
Description  Integrated Multiprotocol Processor User’s Manual
Download  480 Pages
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Maker  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com
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MC68302FC20 Datasheet(HTML) 69 Page - Motorola, Inc

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System Integration Block (SIB)
MOTOROLA
MC68302 USER’S MANUAL
3-19
Table 3-3 indicates the interrupt levels available in both normal and dedicated modes. This
table also shows the IPL2–IPL0 encoding that should be provided by external logic for each
EXRQ interrupt level in normal mode. For the dedicated mode, this table shows the IMP in-
put pins (IRQ7, IRQ6, and IRQ1) that should be asserted by an external device according
to the desired interrupt priority level.
* Priority level not available to an external device in this mode.
3.2.2.2 INRQ Interrupt Source Priorities
Although all INRQ interrupts are presented at level 4, the interrupt controller further organiz-
es interrupt servicing of the 15 INRQ interrupts according to the priorities illustrated in Table
3-4. The interrupt from the port B pin 11 (PB11) has the highest priority, and the interrupt
from the port B pin 8 (PB8) has the lowest priority. A single interrupt priority within level 4 is
associated with each table entry. The IDMA entry is associated with the general-purpose
DMA channel only, and not with the SDMA channels that service the SCCs. Those interrupts
are reported through each individual SCC channel or, in the case of a bus error, through the
SDMA channels bus error entry.
3.2.2.3 Nested Interrupts
The following rules apply to nested interrupts:
1. The interrupt controller responds to all EXRQ and INRQ interrupts based upon their
assigned priority level. The highest priority interrupt request is presented to the
M68000 core for servicing. After the vector number corresponding to this interrupt is
passed to the core during an interrupt acknowledge cycle, an INRQ interrupt request
is cleared in IPR. (EXRQ requests must be cleared externally.) The remaining interrupt
Table 3-3. EXRQ and INRQ Prioritization
Priority
Level
Normal Mode
IPL2–IPL0
Dedicated Mode
IRQ7, IRQ6, IRQ1
Interrupt
Source
7 (Highest)
6
5
4
3
2
1 (Lowest)
000
001
010
*
100
101
110
IRQ7
IRQ6
*
*
*
*
IRQ1
EXRQ
EXRQ
EXRQ
INRQ
EXRQ
EXRQ
EXRQ
Table 3-4. INRQ Prioritization within Interrupt Level 4
Priority
Level
Interrupt Source Description
Multiple
Interrupt
Events
Highest
Lowest
General-Purpose Interrupt 3 (PB11)
General-Purpose Interrupt 2 (PB10)
SCC1
SDMA Channels Bus Error
IDMA Channel
SCC2
Timer 1
SCC3
General-Purpose Interrupt 1 (PB9)
Timer 2
SCP
Timer 3
SMC1
SMC2
General-Purpose Interrupt 0 (PB8)
Error
No
No
Yes
No
Yes
Yes
Yes
Yes
No
Yes
No
No
No
No
No


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