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MC68302FC20 Datasheet(PDF) 68 Page - Motorola, Inc

Part No. MC68302FC20
Description  Integrated Multiprotocol Processor User’s Manual
Download  480 Pages
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Maker  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com
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MC68302FC20 Datasheet(HTML) 68 Page - Motorola, Inc

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System Integration Block (SIB)
3-18
MC68302 USER’S MANUAL
MOTOROLA
Dedicated Mode
In this mode, the three interrupt request pins are configured as IRQ7, IRQ6, and IRQ1 to
provide dedicated request lines for three external sources at priority levels 1, 6, and 7.
Each of these lines may be programmed to be edge-triggered or level-sensitive. In addi-
tion to level 4, which is reserved for INRQ interrupts, interrupt priority levels 2, 3, and 5
must not be assigned to external devices in this mode.
All INRQ and EXRQ sources are prioritized within the interrupt controller. The M68000 sup-
ports seven priority levels. Level 7, the highest priority level, is nonmaskable. EXRQ sources
are given their own separate priority level. Priority level 4 is reserved exclusively for the
INRQ sources with all the INRQ sources being further prioritized within this level. If more
than one INRQ or EXRQ interrupt request is pending, the interrupt controller presents the
highest priority interrupt to the M68000 core through an internal, hidden set of IPL2–IPL0
lines.
When the M68000 core executes the interrupt acknowledge cycle, a vector must be provid-
ed. If an INRQ source generated the interrupt, the interrupt controller always provides the
vector. If an EXRQ source generated the interrupt, three options are available to generate
the vector.
First, in most cases the interrupt controller can be configured to provide the vector to the
M68000 core. This is usually the preferred solution.
Second, the external peripheral can generate the vector. To assist this process, the interrupt
controller can provide up to three interrupt acknowledge outputs (IACK7, IACK6, and
IACK1).
Third, the external peripheral can assert the autovector (AVEC) pin to cause the M68000 to
use an autovector. The autovector method maps each interrupt level to a fixed vector loca-
tion in the exception vector table, regardless of how many interrupt sources exist at that lev-
el.
To improve interrupt latency timing, a fast interrupt latency technique is supported in the
IMP. On recognition of an interrupt, the IMP can assert the bus clear (BCLR) signal exter-
nally, which can be used to force other bus masters off the bus. This involves the IPA and
BCLM bits in the system control register (see 3.8 System Control).
3.2.2 Interrupt Priorities
INRQ and EXRQ interrupts are assigned to an interrupt priority level. INRQ interrupts are
also assigned relative priorities within their given interrupt priority level. A fully nested inter-
rupt environment is provided so that a higher priority interrupt is serviced before a lower pri-
ority interrupt.
3.2.2.1 INRQ and EXRQ Priority Levels
Seven levels of interrupt priority may be implemented in IMP system designs, with level 7
having the highest priority. INRQ interrupts are assigned to level 4 (fixed). EXRQ interrupts
are assigned by the user to any of the remaining six priority levels in normal mode. In dedi-
cated mode, EXRQ interrupts may be assigned to priority levels 7, 6, and 1.


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