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MC68302FC20 Datasheet(PDF) 64 Page - Motorola, Inc

Part No. MC68302FC20
Description  Integrated Multiprotocol Processor User’s Manual
Download  480 Pages
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Maker  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com

MC68302FC20 Datasheet(HTML) 64 Page - Motorola, Inc

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System Integration Block (SIB)
3.1.6 DMA Bus Arbitration
The IDMA controller uses the M68000 bus arbitration protocol to request bus mastership be-
fore entering the DMA mode of operation. The six SDMA channels have priority over the
IDMA and can transfer data between any two IDMA bus cycles with BGACK remaining con-
tinuously low. Once the processor has initialized and started a DMA channel, an operand
transfer request is made pending by either an external device or by using an internal re-
When the IDMA channel has an operand transfer request pending and BCLR is not assert-
ed, the IDMA will request bus mastership from the internal bus arbiter using the internal sig-
nal IDBR (see Figure 3-12). The arbiter will assert the internal M68000 core bus request
(CBR) signal and will monitor the core bus grant (CBG) and external BR to determine when
it may grant the IDMA mastership. The IDMA will monitor the address strobe (AS), HALT,
bus error (BERR), and bus grant acknowledge (BGACK) signals. These signals must be ne-
gated to indicate that the previous bus cycle has completed and the previous bus master
has released the bus. When these conditions are met, the IDMA only asserts BGACK to in-
dicate that it has taken control of the bus. When all operand transfers have occurred, the
IDMA will release control of the bus by negating BGACK.
Internally generated IDMA requests are affected by a mechanism supported to reduce the
M68000 core interrupt latency and external bus master arbitration latency (see 3.8.5 Bus Ar-
bitration Logic). The IDMA is forced to relinquish the bus when an external bus master re-
quests the bus (BR is asserted) or when the M68000 core has an unmasked pending
interrupt request. In these cases, the on-chip arbiter sends an internal bus-clear signal to
the IDMA. In response, any operand transfer in progress will be fully completed (up to four
bus cycles depending on the configuration), and bus ownership will be released.
When the IDMA regains the bus, it will continue transferring where it left off. If the core
caused the bus to be relinquished, no further IDMA bus cycles will be started until IPA in the
SCR is cleared. If the cause was an external request, no further IDMA bus cycles will be
started while BR remains asserted. When BR is externally negated, if a transfer request is
pending and IPA is cleared, the IDMA will arbitrate for the bus and continue normal opera-
3.1.7 Bus Exceptions
In any computer system, the possibility always exists that an error will occur during a bus
cycle due to a hardware failure, random noise, or an improper access. When an asynchro-
nous bus structure, such as that supported by the M68000 is used, it is easy to make provi-
sions allowing a bus master to detect and respond to errors during a bus cycle. The IDMA
recognizes the same bus exceptions as the M68000 core: reset, bus error, halt, and retry.
These exceptions also apply to the SDMA channels except that
the bus error reporting method is different. See Bus Error
on SDMA Access for further details.

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