Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

MC68302FC20 Datasheet(PDF) 54 Page - Motorola, Inc

Part No. MC68302FC20
Description  Integrated Multiprotocol Processor User’s Manual
Download  480 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com
Logo 

MC68302FC20 Datasheet(HTML) 54 Page - Motorola, Inc

Zoom Inzoom in Zoom Outzoom out
 54 / 480 page
background image
System Integration Block (SIB)
3-4
MC68302 USER’S MANUAL
MOTOROLA
(DAPR), an 8-bit function code register (FCR), a 16-bit byte count register (BCR), a 16-bit
channel mode register (CMR), and an 8-bit channel status register (CSR). These registers
provide the addresses, transfer count, and configuration information necessary to set up a
transfer. They also provide a means of controlling the IDMA and monitoring its status. All
registers can be modified by the M68000 core. The IDMA also includes another 16-bit reg-
ister, the data holding register (DHR), which is not accessible to the M68000 core and is
used by the IDMA for temporary data storage.
3.1.2.1 Channel Mode Register (CMR)
The CMR, a 16-bit register, is reset to $0000.
Bit 15—Reserved for future use.
ECO—External Control Option
0 = If the request generation is programmed to be external in the REQG bits, the con-
trol signals (DACK and DONE) are used in the source (read) portion of the transfer
since the peripheral is the source.
1 = If the request generation is programmed to be external in the REQG bits, the con-
trol signals (DACK and DONE) are used in the destination (write) portion of the
transfer since the peripheral is the destination.
INTN—Interrupt Normal
0 = When the channel has completed an operand transfer without error conditions as
indicated by DONE, the channel does not generate an interrupt request to the IMP
interrupt controller. The DONE bit remains set in the CSR.
1 = When the channel has completed an operand transfer without error conditions as
indicated by DONE, the channel generates an interrupt request to the IMP interrupt
controller and sets DONE in the CSR.
NOTE
An interrupt will only be generated if the IDMA bit is set in the in-
terrupt mask register (IMR).
INTE—Interrupt Error
0 = If a bus error occurs during an operand transfer either on the source read (BES) or
the destination write (BED), the channel does not generate an interrupt to the IMP
interrupt controller. The appropriate bit remains set in the CSR.
1 = If a bus error occurs during an operand transfer either on BES or BED, the channel
generates an interrupt to the IMP interrupt controller and sets the appropriate bit
(BES or BED) in the CSR.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ECO
INTN
INTE
REQG
SAPI
DAPI
SSIZE
DSIZE
BT
RST
STR


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61  62  63  64  65  66  67  68  69  70  71  72  73  74  75  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90  91  92  93  94  95  96  97  98  99  100   ...More


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn