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MC68302FC20 Datasheet(PDF) 52 Page - Motorola, Inc

Part No. MC68302FC20
Description  Integrated Multiprotocol Processor User’s Manual
Download  480 Pages
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Maker  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com
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MC68302FC20 Datasheet(HTML) 52 Page - Motorola, Inc

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System Integration Block (SIB)
3-2
MC68302 USER’S MANUAL
MOTOROLA
3.1 DMA CONTROL
The IMP includes seven on-chip DMA channels, six serial DMA (SDMA) channels for the
three serial communications controllers (SCCs) and one IDMA. The SDMA channels are
discussed in 4.2 SDMA Channels. The IDMA is discussed in the following paragraphs.
3.1.1 Key Features
The IDMA (Independent DMA Controller) has the following key features:
• Two Address Pointers and One Counter
• Support of Memory-to-Memory, Peripheral-to-Memory, and Memory-to-Peripheral Data
Transfers
• Three I/O Lines, DREQ, DACK, and DONE, for Externally Requested Data Transfers
• Asynchronous M68000 Bus Structure with 24-Bit Address and 8-Bit or 16-Bit Data Bus
• Support for Data Blocks Located at Even or Odd Addresses
• Packing and Unpacking of Operands
• Fast Transfer Rates: Up to 4M bytes/second at 16.0 MHz with No Wait States
• Full Support of All M68000 Bus Exceptions: Halt, Bus Error, Reset, and Retry
• Flexible Request Generation:
—Internal, Maximum Rate (One Burst)
—Internal, Limited Rate (Limited Burst Bandwidth)
—External, Burst (DREQ Level Sensitive)
—External, Cycle Steal (DREQ Edge Sensitive)
The one general-purpose IDMA controller can operate in different modes of data transfer as
programmed by the user. The IDMA is capable of transferring data between any combina-
tion of memory and I/O. In addition, data may be transferred in either byte or word quantities,
and the source and destination addresses may be either odd or even. Note that the chip se-
lect and wait state generation logic on the MC68302 may be used with the IDMA, if desired.
Every IDMA cycle requires between two and four bus cycles, depending on the address
boundary and transfer size. Each bus cycle is a standard M68000-type read or write cycle.
If both the source and destination addresses are even, the IDMA fetches one word of data
and immediately deposits it. If either the source or destination address begins on an odd
boundary, the transfer is handled differently. For example, if the source address starts on an
odd boundary and the destination address is even, the IDMA reads one byte from the
source, then reads the second byte from the source, and finally stores the word in a single
access. If the source is even and the destination odd, then the IDMA will read one word from
the source and store it in two consecutive cycles. If both the source and destination are odd,
the IDMA performs two read byte cycles followed by two write byte cycles until the transfer
is complete.
If the IMP frequency is 16.0 MHz and zero wait state memory is used, then the maximum
transfer rate is 4M byte/sec. This assumes that the operand size is 16-bits, the source and
destination addresses are even, and the bus width is selected to be 16-bits.


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