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MC68302FC20 Datasheet(PDF) 49 Page - Motorola, Inc

Part No. MC68302FC20
Description  Integrated Multiprotocol Processor User’s Manual
Download  480 Pages
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Maker  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com
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MC68302FC20 Datasheet(HTML) 49 Page - Motorola, Inc

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MC68000/MC68008 Core
MOTOROLA
MC68302 USER’S MANUAL
2-19
#
Reset only upon a total system reset (RESET and HALT assert together), but not on the execution of an M68000
RESET instruction. See the RESET pin description for details.
## The output latches are undefined at total system reset.
!
Event register with special properties (see 2.9 Event Registers).
2.9 EVENT REGISTERS
The IMP contains a few special registers designed to report events to the user. They are the
channel status register (CSR) in the independent DMA, the interrupt pending register (IPR)
and interrupt in-service register (ISR) in the interrupt controller, the timer event register 1
(TER1) in timer 1, the TER2 in timer 2, serial communication controller event register 1
(SCCE1) in SCC1, SCCE2 in SCC2, and SCCE3 in SCC3. Events in these register are al-
ways reported by a bit being set.
During the normal course of operation, the user software will clear these events after recog-
nizing them. To clear a bit in one of these registers, the user software must WRITE A ONE
TO THAT BIT. Writing a zero has no effect on the register. Thus, in normal operation, the
hardware only
sets bits in these registers; whereas, the software only clears them.
This technique prevents software from inadvertently losing the indication from an event bit
that is “set” by the hardware between the software read and the software write of this regis-
ter.
All these registers are cleared after a total system reset (RESET and HALT asserted togeth-
er) and after the M68000 RESET instruction. Also some of the blocks (IDMA, timer1, timer2,
and communication processor) have a reset (RST) bit located in a register in that block. This
RST bit will reset that entire block, including any event registers contained therein.
Examples:
1. To clear bit 0 of SCCE1, execute "MOVE.B #$01,SCCE1"
Base + 8A0
Base + 8A2
Base + 8A4
Base + 8A6
! Base + 8A8
Base + 8A9
Base + 8AA
Base + 8AB
Base + 8AC
Base + 8AD
Base + 8AE
RES
SCON3
SCM3
DSR3
SCCE3
RES
SCCM3
RES
SCCS3
RES
RES
16
16
16
16
8
8
8
8
8
8
16
SCC3
SCC3
SCC3
SCC3
SCC3
SCC3
SCC3
SCC3
SCC3
SCC3
SCC3
Reserved
SCC3 Configuration Register
SCC3 Mode Register
SCC3 Data Sync. Register
SCC3 Event Register
Reserved
SCC3 Mask Register
Reserved
SCC3 Status Register
Reserved
Reserved
0004
0000
7E7E
00
00
00
Base + 8B0
SPMODE
16
SCM
SCP, SMC Mode and Clock
Control Register
0000
Base + 8B2 #
Base + 8B4 #
SIMASK
SIMODE
16
16
SI
SI
Serial Interface Mask Register
Serial Interface Mode Register
FFFF
0000
Base + 8B6
Base + FFF
Reserved
(Not Implemented)
Table 2-9. Internal Registers


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