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MC68302FC20 Datasheet(PDF) 41 Page - Motorola, Inc

Part No. MC68302FC20
Description  Integrated Multiprotocol Processor User’s Manual
Download  480 Pages
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Maker  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com

MC68302FC20 Datasheet(HTML) 41 Page - Motorola, Inc

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MC68000/MC68008 Core
Seven interrupt levels are provided by the M68000 core. If the IMP's interrupt controller is
placed in the normal mode, six levels are available to the user. If the interrupt controller is in
the dedicated mode, three levels are available to the user. In either mode, level 4 is reserved
for the on-chip peripherals. Devices may be chained externally within one of the available
priority levels, allowing an unlimited number of external peripheral devices to interrupt the
processor. The SR contains a 3-bit mask indicating the current processor priority level. In-
terrupts are inhibited for all priority levels less than or equal to the current processor priority
(see Figure 2-2).
An interrupt request is made to the processor by encoding the request on the interrupt re-
quest lines (normal mode) or by asserting the appropriate request line (dedicated mode).
Rather than forcing immediate exception processing, interrupt requests arriving at the pro-
cessor are made pending to be detected between instruction executions.
If the priority of the pending interrupt is lower than or equal to the current processor priority,
execution continues with the next instruction, and the interrupt exception processing is post-
If the priority of the pending interrupt is greater than the current processor priority, the ex-
ception processing sequence is started. A copy of the SR is saved, the privilege state is set
to supervisor state, tracing is suppressed, and the processor priority level is set to the level
of the interrupt being acknowledged. The processor fetches the vector number from the in-
terrupting device, classifying the reference as an interrupt acknowledge on the address bus.
If external logic requests automatic vectoring (via the AVEC pin), the processor internally
generates a vector number determined by the interrupt level number. If external logic indi-
cates a bus error, the interrupt is considered spurious, and the generated vector number ref-
erences the spurious interrupt vector number.
The MC68302 core supports one additional signal not visible on the standard M68000:
RMC. Asserted externally on read-modify-write cycles, the RMC signal is typically used as
a bus lock to ensure integrity of instructions using the locked read-modify-write operation of
the test and set (TAS) instruction. The RMC signal from the M68000 core is applied to the
MC68302 arbiter and can be programmed to prevent the arbiter from issuing bus grants until
the completion of an MC68000-core-initiated read-modify-write cycle.
The MC68302 can be programmed to use the RMC signal to negate address strobe (AS) at
the end of the read portion of the cycle and assert AS at the beginning of the write portion
of the cycle (See 3.8.3 System Control Bits).
Two M6800 signals are omitted from the MC68302: valid memory address (VMA) and en-
able (E). The valid peripheral address (VPA) signal is retained, but is only used on the
MC68302 as AVEC to direct the core to use an autovector during interrupt acknowledge cy-

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