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MC68302FC20 Datasheet(PDF) 38 Page - Motorola, Inc

Part No. MC68302FC20
Description  Integrated Multiprotocol Processor User’s Manual
Download  480 Pages
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Maker  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com
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MC68302FC20 Datasheet(HTML) 38 Page - Motorola, Inc

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MC68000/MC68008 Core
2-8
MC68302 USER’S MANUAL
MOTOROLA
Once the processor is in the user state and executing instructions, only exception process-
ing can change the privilege state. During exception processing, the current state of the S
bit in the SR is saved and the S bit is asserted, putting the processor in the supervisor state.
Therefore, when instruction execution resumes at the address specified to process the ex-
ception, the processor is in the supervisor privilege state. The transition from the supervisor
to user state can be accomplished by any of four instructions: return from exception (RTE),
move to status register (MOVE to SR), AND immediate to status register (ANDI to SR), and
exclusive OR immediate to status register (EORI to SR).
2.4 EXCEPTION PROCESSING
The processing of an exception occurs in four steps, with variations for different exception
causes. During the first step, a temporary copy of the SR is made, and the SR is set for ex-
ception processing. During the second step, the exception vector is determined; during the
third step, the current processor context is saved. During the fourth step, a new context is
obtained, and the processor switches to instruction processing.
2.4.1 Exception Vectors
Exception vectors are memory locations from which the processor fetches the address of a
routine to handle that exception. All exception vectors are two words long except for the re-
set vector, which is four words. All exception vectors lie in the supervisor data space except
for the reset vector, which is in the supervisor program space. A vector number is an 8-bit
number which, when multiplied by four, gives the offset of the exception vector. Vector num-
bers are generated internally or externally, depending on the cause of the exception. In the
case of interrupts, during the interrupt acknowledge bus cycle, a peripheral may provide an
8-bit vector number to the processor on data bus lines D7–D0. Alternatively, the peripheral
may assert autovector (AVEC) instead of data transfer acknowledge (DTACK) to request an
autovector for that priority level of interrupt. The exception vector assignments for the
M68000 processor are shown in Table 2-5.
Table 2-5. M68000 Exception Vector Assignment
Vector
Number
Decimal
Address
Hex
Space
Assignment
0
0
000
SP
Reset: Initial SSP2
1
4
004
SP
Reset: Initial PC2
2
8
008
SD
Bus Error
3
12
00C
SD
Address Error
4
16
010
SD
Illegal Instruction
5
20
014
SD
Zero Divide
6
24
018
SD
CHK Instruction
7
28
01C
SD
TRAPV Instruction
8
32
020
SD
Privilege Violation
9
36
024
SD
Trace
10
40
028
SD
Line 1010 Emulator


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