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MC68302RC16 Datasheet(PDF) 27 Page - Motorola, Inc |
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MC68302RC16 Datasheet(HTML) 27 Page - Motorola, Inc |
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27 / 480 page  General Description MOTOROLA MC68302 USER’S MANUAL 1-5 Figure 1-3. MC68302 System Design The use of a unique arbitration scheme and synchronous transfers between the micropro- cessor and dual-port RAM gives zero wait-state operation to the M68000 microprocessor core. The dual-port RAM can be accessed by the CP main controller (RISC) once every clock cycle for either read or write operations. When the M68000 core accesses the dual- port RAM, each access is pipelined along with the CP accesses so that data is read or writ- ten without conflict. The net effect is the loss of a single memory access by the CP main controller per M68000 core access. The buffer memory structure of the MC68302 can be configured to closely match I/O chan- nel requirements by careful selection of buffer size and buffer linking. The interrupt structure is also programmable so that the on-chip M68000 processor can be off-loaded from the pe- ripheral bit-handling functions to perform higher layer application software or protocol pro- cessing. 1.4 NMSI COMMUNICATIONS-ORIENTED ENVIRONMENT When the interface to equipment or proprietary networks requires the use of standard con- trol and data signals, the MC68302 can be programmed into the nonmultiplexed serial inter- face (NMSI) mode. This mode, which is available for one, two, or all three SCC ports, can be selected while the other ports use one of the multiplexed interface modes (IDL, GCI, or PCM highway). PERIPHERAL BUS 68000 SYSTEM BUS MC68302 IMP 6 DMA CHANNELS INTERRUPT CONTROLLER MICROCODED COMMUNICATIONS CONTROLLER (RISC) M68000 CORE 1 GENERAL- PURPOSE DMA CHANNEL 3 TIMERS AND ADDITIONAL FEATURES RAM / ROM OTHER PERIPHERALS OTHER SERIAL CHANNELS 1152 BYTES DUAL-PORT RAM 3 SERIAL CHANNELS |
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