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LMX2305 Datasheet(PDF) 2 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. LMX2305
Description  PLLatinumTM 550 MHz Frequency Synthesizer for RF Personal Communications
Download  14 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

LMX2305 Datasheet(HTML) 2 Page - National Semiconductor (TI)

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Connection Diagram
LMX2305
TLW12459 – 2
20-Lead (0173 Wide) Thin Shrink
Small Outline Package (TM)
Order Number LMX2305TM or LMX2305TMX
See NS Package Number MTC20
Pin Descriptions
Pin No
Pin Name
IO
Description
1
OSCIN
I
Oscillator input A CMOS inverting gate input intended for connection to a crystal resonator for
operation as an oscillator The input has a VCC 2 input threshold and can be driven from an
external CMOS or TTL logic gate May also be from a reference oscillator
3
OSCOUT
O
Oscillator output
4VP
Power supply for charge pump Must be t VCC
5VCC
Power supply voltage input Input may range from 265V to 55V Bypass capacitors should be
placed as close as possible to this pin and be connected directly to the ground plane
6Do
O
Internal charge pump output For connection to a loop filter for driving the input of an external
VCO
7
GND
Ground
8
LD
O
Lock detect Output provided to indicate when the VCO frequency is in ‘‘lock’’ When the loop is
locked the pin’s output is HIGH with narrow low pulses
10
fIN
I
Prescaler input Small signal input from the VCO
11
CLOCK
I
High impedance CMOS Clock input Data is clocked in on the rising edge into the various
counters and registers
13
DATA
I
Binary serial data input Data entered MSB first LSB is control bit High impedance CMOS input
14
LE
I
Load enable input (with internal pull-up resistor) When LE transitions HIGH data stored in the
shift registers is loaded into the appropriate latch (control bit dependent) Clock must be low
when LE toggles high or low See Serial Data Input Timing Diagram
15
FC
I
Phase control select (with internal pull-up resistor) When FC is LOW the polarity of the phase
comparator and charge pump combination is reversed
16
BISW
O
Analog switch output When LE is HIGH the analog switch is ON routing the internal charge
pump output through BISW (as well as through Do)
17
fOUT
O
Monitor pin of phase comparator input CMOS output
18
wp
O
Output for external charge pump wp is an open drain N-channel transistor and requires a pull-up
resistor
19
PWDN
I
Power Down (with internal pull-up resistor)
PWDN e HIGH for normal operation
PWDN e LOW for power saving
Power down function is gated by the return of the charge pump to a TRI-STATE condition
20
wr
O
Output for external charge pump wr is a CMOS logic output
2912
NC
No connect
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www nationalcom
2


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