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LMX2305 Datasheet(PDF) 13 Page - National Semiconductor (TI) |
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LMX2305 Datasheet(HTML) 13 Page - National Semiconductor (TI) |
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13 / 14 page  Application Information (Continued) EXTERNAL CHARGE PUMP The LMX PLLatinum series of frequency synthesizers are equipped with an internal balanced charge pump as well as outputs for driving an external charge pump Although the superior performance of NSC’s on board charge pump elim- inates the need for an external charge pump in most appli- cations certain system requirements are more stringent In these cases using an external charge pump allows the de- signer to take direct control of such parameters as charge pump voltage swing current magnitude TRI-STATE leak- age and temperature compensation One possible architecture for an external charge pump cur- rent source is shown in Figure 9 The signals wp and wr in the diagram correspond to the phase detector outputs of the LMX2305 frequency synthesizer These logic signals are converted into current pulses using the circuitry shown in Figure 9 to enable either charging or discharging of the loop filter components to control the output frequency of the PLL Referring to Figure 9 the design goal is to generatea5mA current which is relatively constant to within 05V of the power supply rail To accomplish this it is important to es- tablish as large of a voltage drop across R5 R8 as possible without saturating Q2 Q4 A voltage of approximately 300 mV provides a good compromise This allows the current source reference being generated to be relatively repeat- able in the absence of good Q1 Q2Q3 Q4 matching (Matched transistor pairs is recommended) The wp and wr outputs are rated for a maximum output load current of 1 mA while 5 mA current sources are desired The voltages developed across R4 9 will consequently be approximately 258 mV or 42 mV k R8 5 due to the current density differ- ences 0026 1n (5 mA1 mA) through the Q1 Q2Q3 Q4 pairs In order to calculate the value of R7 it is necessary to first estimate the forward base to emitter voltage drop (Vfnp) of the transistors used the VOL drop of wp and the VOH drop of wr’s under 1 mA loads (wp’s VOL k 01V and wr’s VOH k 01V) Knowing these parameters along with the desired current allow us to design a simple external charge pump Separat- ing the pump up and pump down circuits facilitates the no- dal analysis and give the following equations R4 e VR5 b VT # ln #isource ip max J isource R9 e VR8 b VT # ln # isink in max J isink R5 e VR5 ip max R8 e VR8 ir max R6 e (Vp b VVOLwp) b (VR5 a Vfp) ip max R7 e (VP b VVOHwr) b (VR8 a Vfn) imax EXAMPLE Typical Device Parameters bn e100 bp e 50 Typical System Parameters VP e 50V Vcntl e 05V b 45V Vwp e 00V Vwr e 50V Design Parameters ISINK e ISOURCE e 50 mA Vfn e Vfp e 08V Irmax e Ipmax e 1mA VR8 e VR5 e 03V VOLwp e VOHwr e 100 mV TLW12459 – 28 FIGURE 9 Therefore select R4 e R9 e 03V b 0026 # 1n(50 mA10 mA) 5mA e 516X R5 e 03V 10 mA e 300X R8 e 03V 10 mA e 300X R6 e R7 e (5V b 01V) b (03V a 08V) 10 mA e 38 kX http www nationalcom 13 |
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