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LMX1600 Datasheet(PDF) 6 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. LMX1600
Description  PLLatinum™ Low Cost Dual Frequency Synthesizer
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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LMX1600 Datasheet(HTML) 6 Page - National Semiconductor (TI)

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1.0 Functional Description (Continued)
the phase detector inputs is less than 15 ns for 4 consecutive
comparison cycles. The lock detect output is low when the
error between the phase detector outputs is more than 30 ns
for one comparison cycle. The lock detect output is always
low when the PLL is in power down mode. For further de-
scription see Programming Description 2.5.
1.9
POWER CONTROL
Each PLL is individually power controlled by the device EN
pin. The EN
MAIN controls the Main PLL, and the ENAUX con-
trols the Aux PLL. Activation of EN = LOW (power down)
condition results in the disabling of the respective N and R
counters and de-biasing of their respective fin inputs (to a
high impedance state). The reference oscillator input block
powers down and the OSC
IN pin reverts to a high impedance
state only when both EN pins are LOW. Power down forces
the respective charge pump and phase comparator logic to a
TRI-STATE condition as well as disabling the bandgap refer-
ence block. Power up occurs immediately when the EN pin is
brought high. Power up sequence: Bandgap and Oscillator
blocks come up first, with the remaining PLL functions be-
coming active approx. 1 µs later. All programming informa-
tion is retained internally in the chip when in power down
mode. The MICROWIRE control register remains active and
capable of loading and latching in data during power down
mode.
2.0
Programming Description
2.1
MICROWIRE INTERFACE
The descriptions below detail the 18-bit data register loaded through the MICROWIRE Interface. The 18-bit shift register is used
to program the 12-bit Main and Aux R counter registers and the 16-bit Main and Aux N counter registers. The shift register con-
sists of a 16-bit DATA field and a 2-bit control (CTL [1:0]) field as shown below. The control bits decode the internal register ad-
dress. On the rising edge of LE, data stored in the shift register is loaded into one of the 4 appropriate latches (selected by ad-
dress bits). Data is shifted in MSB first.
MSB
LSB
DATA [15:0]
CTL [1:0]
18
2
1
0
2.1.1
Register Location Truth Table
When LE transitions high, data is transferred from the 18-bit shift register into one of the 4 appropriate internal latches depending
upon the state of the control (CTL) bits. The control bits decode the internal register address
CTL [1:0]
DATA Location
0
0
AUX_R Register
0
1
AUX_N Register
1
0
MAIN_R Register
1
1
MAIN_N Register
2.1.2
Register Content Truth Table
First Bit
SHIFT REGISTER BIT LOCATION
Last Bit
17
16
15
14
13
12
11
10
9876543210
AUX_R
FoLD
AUX_R_CNTR
0
0
AUX_N
AUX_B_CNTR
AUX_A_CNTR
0
1
MAIN_R
CP_WORD
MAIN_R_CNTR
1
0
MAIN_N
MAIN_B_CNTR and MAIN_A_CNTR
1
1
2.2
PROGRAMMABLE REFERENCE DIVIDERS
2.2.1
AUX_R Register
If the Control Bits (CTL [1:0]) are 0 0 when LE transitions high, data is transferred from the 18-bit shift register into a latch which
sets the Aux PLL 12-bit R counter divide ratio. The divide ratio is programmed using the bits AUX_R_CNTR as shown in table
2.2.3. The divider ratio must be
≥ 2. The FoLD word bits controls the multifunction FoLD output as described in section in 2.5.
First Bit
SHIFT REGISTER BIT LOCATION
Last Bit
17
16
15
14
13
12
11
10
9876543210
AUX_R
FoLD[3:0]
AUX_R_CNTR[11:0]
0
0
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