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LMX1501A Datasheet(PDF) 2 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. LMX1501A
Description  PLLatinumTM 1.1 GHz Frequency Synthesizer for RF Personal Communications
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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LMX1501A Datasheet(HTML) 2 Page - National Semiconductor (TI)

 
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Connection Diagrams
LMX1501A
TLW12340 – 2
JEDEC 16-Lead (0150 Wide) Small
Outline Molded Package (M)
Order Number LMX1501AM or LMX1501AMX
See NS Package Number M16A
LMX1511
TLW12340 – 3
20-Lead (0173 Wide) Thin Shrink
Small Outline Package (TM)
Order Number LMX1511TM or LMX1511TMX
See NS Package Number MTC20
Pin Descriptions
Pin No
Pin No
Pin Name
IO
Description
1501A
1511
1501A1511
1
1
OSCIN
I
Oscillator input A CMOS inverting gate input intended for connection to a
crystal resonator for operation as an oscillator The input has a VCC 2 input
threshold and can be driven from an external CMOS or TTL logic gate May also
be used as a buffer for an externally provided reference oscillator
2
3
OSCOUT
O
Oscillator output
34
VP
Power supply for charge pump must be t VCC
45
VCC
Power supply voltage input Input may range from 27V to 55V Bypass
capacitors should be placed as close as possible to this pin and be connected
directly to the ground plane
56
Do
O
Internal charge pump output For connection to a loop filter for driving the input
of an external VCO
6
7
GND
Ground
7
8
LD
O
Lock detect Output provided to indicate when the VCO frequency is in ‘‘lock’’
When the loop is locked the pin’s output is HIGH with narrow low pulses
810
fIN
I
Prescaler input Small signal input from the VCO
9
11
CLOCK
I
High impedance CMOS Clock input Data is clocked in on the rising edge into
the various counters and registers
10
13
DATA
I
Binary serial data input Data entered MSB first LSB is control bit High
impedance CMOS input
11
14
LE
I
Load enable input (with internal pull-up resistor) When LE transitions HIGH
data stored in the shift registers is loaded into the appropriate latch (control bit
dependent) Clock must be low when LE toggles high or low See Serial Data
Input Timing Diagram
12
15
FC
I
Phase control select (with internal pull-up resistor) When FC is LOW the
polarity of the phase comparator and charge pump combination is reversed
X
16
BISW
O
Analog switch output When LE is HIGH the analog switch is ON routing the
internal charge pump output through BISW (as well as through Do)
13
fr
O
Monitor pin of phase comparator input Programmable reference divider output
14
fp
O
Monitor pin of phase comparator input Programmable divider output
X17
fOUT
O
Monitor pin of phase comparator input CMOS Output
15
18
wp
O
Output for external charge pump wp is an open drain N-channel transistor and
requires a pull-up resistor
16
20
wr
O
Output for external charge pump wr is a CMOS logic output
X
291219
NC
No connect
2


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