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AK7755 Datasheet(PDF) 45 Page - Asahi Kasei Microsystems |
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AK7755 Datasheet(HTML) 45 Page - Asahi Kasei Microsystems |
45 / 109 page [AK7755] 014006643-E-00 2014/10 - 45 - CONT10: Function Settings W R Name D7 D6 D5 D4 D3 D2 D1 D0 Default D0h 50h CONT10 WDTEN CRCE PLLLOCKE SOCFG SELSTO 0 0 CKADJEN 00h D7: WDTEN WDT (watchdog timer) Setting 0: WDTE Enable (default) 1: WDTE Disable D6: CRCE CRC (cyclic redundancy check) Setting 0: CRC Disable (default) 1: CRC Enable D5: PLLLOCKE PLL LOCK Detection 0: PLL LOCK Disable (default) 1: PLL LOCK Enable D4: SOCFG SO pin Hi-Z Select 0: Hi-Z (default) 1: CMOSL D3: SELSTO STO/RDY Pin Selecting Status Out 0: STO (default) 1: RDY D0: CKADJEN Clock Adjustment Enable 0: CKADJ DISABLE (default) 1: CKADJ ENABLE Write this bit to “1” when setting CONT11 CKADJ[7:0] bits. Write “0” into the “0” registers. CONT11: DSPMCLK Availability Ratio Setting W R Name D7 D6 D5 D4 D3 D2 D1 D0 Default D1h 51h CONT11 CK ADJ[7]) CK ADJ[6]) CK ADJ[5]) CK ADJ[4]) CK ADJ[3]) CK ADJ[2]) CK ADJ[1]) CK ADJ[0]) 00h D7-D0: CKADJ [7:0] DSPMCLK Availability Ratio Setting Availability = (256-CKADJ) / 256 0000_0000: 100% driving (Normal) (default) 0000_0001: 99.6% driving • • • 1000_0000: 50% driving • • • 1111_1110: 0.8% driving 1111_1111: 0.4% driving Set CONT10 CKADJEN bit to “1” when using this register. DSPMCLK must always be more than 10 times of SCLK. For example, when SCLK is 2MHz, the setting should be lower than 0hD6 (214) since CKADJ[7:0] < 256 – (2 x 10 x 256) / 122.88 = 214.33. |
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