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IDT72V18320 Datasheet(PDF) 3 Page - Integrated Device Technology |
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IDT72V18320 Datasheet(HTML) 3 Page - Integrated Device Technology |
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3 / 26 page  3 INDUSTRIAL TEMPERATURE RANGE IDT72V15160/16160/17160/18160/19160 - 3.3V 16-BIT V-III MULTIMEDIA FIFO IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO TQFP: (PK128-1, order code: PF) TOP VIEW The Partial Reset ( PRS) also sets the read and write pointers to the first locationofthememory.However,theprogrammableflagsettingsexistingbefore Partial Reset remain unchanged. PRS is useful for resetting a device in mid- operation, when reprogramming programmable flags would be undesirable. Itisalsopossibletoselectthetimingmodeofthe PAE(ProgrammableAlmost- Empty flag) and PAF (Programmable Almost-Full flag) outputs. The timing modes can be set to be either asynchronous or synchronous for the PAEand PAFflags. If asynchronous PAE/PAF configuration is selected, thePAE is asserted LOWontheLOW-to-HIGHtransitionofRCLK. PAEisresettoHIGHontheLOW- to-HIGH transition of WCLK. Similarly, the PAFisassertedLOWontheLOW- to-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK. Ifsynchronous PAE/PAFconfigurationisselected,thePAEisassertedand updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is assertedandupdatedontherisingedgeofWCLKonlyandnotRCLK.Themode desiredisconfiguredduringMasterResetbythestateoftheProgrammableFlag Mode (PFM) pin. If, at any time, the FIFO is not actively performing an operation, the chip will automatically power down. Once in the power down state, the standby supply currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol inputs) will immediately take the device out of the power down state. The IDT V-III and Vx-III family of FIFOs are fabricated using IDT’s high speed submicron CMOS technology. PIN CONFIGURATIONS (32-BIT Vx-III FAMILY) VCC OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 GND D4 VCC D5 GND D6 D7 D8 GND D9 D10 GND GND D11 D12 D13 D14 D15 GND D16 D17 GND VCC D19 D20 GND D21 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 102 101 Q0 GND GND Q4 Q5 Q6 Q7 Q8 DNC(1) Q9 Q10 GND GND DNC(1) Q11 Q12 Q13 Q14 Q15 GND Q16 Q17 DNC(1) Q18 Q19 Q20 GND Q21 Q22 INDEX WEN SEN DNC(1) D18 VCC VCC VCC VCC VCC VCC DNC(1) D0 D1 D2 D3 Q1 Q2 Q3 6163 drw03 NOTE: 1. DNC - Do Not Connect. |
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