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IDT74LVC125A Datasheet(PDF) 2 Page - Integrated Device Technology

Part No. IDT74LVC125A
Description  3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT74LVC125A Datasheet(HTML) 2 Page - Integrated Device Technology

   
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INDUSTRIALTEMPERATURERANGE
2
IDT74LVC125A
3.3VCMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
NOTE:
1. As applicable to the device type.
Symbol
Parameter(1)
Conditions
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0V
4.5
6
pF
COUT
Output Capacitance
VOUT = 0V
5.5
8
pF
CI/O
I/O Port Capacitance
VIN = 0V
6.5
8
pF
CAPACITANCE (TA= +25°C, F = 1.0MHz)
Symbol
Description
Max
Unit
VTERM
Terminal Voltage with Respect to GND
–0.5 to +6.5
V
TSTG
Storage Temperature
–65 to +150
°C
IOUT
DC Output Current
–50 to +50
mA
IIK
Continuous Clamp Current,
–50
mA
IOK
VI < 0 or VO < 0
ICC
Continuous Current through each
±100
mA
ISS
VCC or GND
ABSOLUTE MAXIMUM RATINGS(1)
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
PIN CONFIGURATION
PIN DESCRIPTION
Pin Names
Description
xOE
Output-Enable Inputs (Active LOW)
x A
DataInputs
x Y
3-StateOutputs
1
OE
1
A
1
Y
2
OE
2
A
2
Y
GND
2
3
4
5
6
7
8
9
10
11
12
13
14
1
VCC
4
A
3
A
3
Y
4
Y
4
OE
3
OE
SOIC/ SSOP/ TSSOP
TOP VIEW
FUNCTION TABLE (EACHBUFFER)(1)
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-Impedance
Inputs
Outputs
xOE
xA
xY
LH
H
LL
L
HX
Z


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