64K x 32 Synchronous-Pipelined Cache RAM
CY7C1329
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
August 6, 1999
Features
• Supports 133-MHz bus for Pentium® and PowerPC™
operations with zero wait states
• Fully registered inputs and outputs for pipelined
operation
• 64K x 32 common I/O architecture
• Single 3.3V power supply
• Fast clock-to-output times
— 4.2 ns (for 133-MHz device)
— 5.5 ns (for 100-MHz device)
— 7.0 ns (for 75-MHz device
• User-selectable burst counter supporting Intel®
Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• JEDEC-standard 100 TQFP pinout
• “ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1329 is a 3.3V, 64K by 32 synchronous-pipelined
cache SRAM designed to support zero wait state secondary
cache with minimal glue logic.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Max-
imum access delay from the clock rise is 4.2 ns (133-MHz
device).
The CY7C1329 supports either the interleaved burst se-
quence used by the Intel Pentium processor or a linear burst
sequence used by processors such as the PowerPC. The burst
sequence is selected through the MODE pin. Accesses can
be initiated by asserting either the Processor Address Strobe
(ADSP) or the Controller Address Strobe (ADSC) at clock rise.
Address advancement through the burst sequence is con-
trolled by the ADV input. A 2-bit on-chip wraparound burst
counter captures the first address in a burst sequence and
automatically increments the address for the rest of the burst
access.
Byte write operations are qualified with the four Byte Write
Select (BW[3:0]) inputs. A Global Write Enable (GW) overrides
all byte write inputs and writes data to all four bytes. All writes
are conducted with on-chip synchronous self-timed write cir-
cuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to provide prop-
er data during depth expansion, OE is masked during the first
clock of a read cycle when emerging from a deselected state.
Intel and Pentium are registered trademarks of Intel Corporation.
PowerPC is a trademark of IBM Corporation.
CLK
ADV
ADSC
A[15:0]
GW
BWE
BW 3
BW
2
BW1
BW0
CE1
CE3
CE2
OE
ZZ
BURST
COUNTER
DQ[31:24]
BYTEWRITE
REGISTERS
ADDRESS
REGISTER
D
Q
OUTPUT
REGISTERS
INPUT
REGISTERS
64KX32
MEMORY
ARRAY
CLK
CLK
Q0
Q1
Q
D
CE
CE
CLR
SLEEP
CONTROL
DQ[23:16]
BYTEWRITE
REGISTERS
D
Q
DQ
DQ[15:8]
BYTEWRITE
REGISTERS
DQ[7:0]
BYTEWRITE
REGISTERS
D
Q
ENABLE
REGISTER
D
Q
CE
CLK
ENABLE DELAY
REGISTER
D
Q
CLK
32
32
16
14
14
16
(A[1:0])
2
MODE
ADSP
Logic Block Diagram
DQ[31:0]