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CS7808-CM Datasheet(PDF) 14 Page - Cirrus Logic |
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CS7808-CM Datasheet(HTML) 14 Page - Cirrus Logic |
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14 / 52 page 
CS7808 14 1.2.7 Audio Output Interface Symbol Description Min Typ Max Units taxch AUD_XCLK High Time (AUD_XCLK is Input/Output)1, 2 1.Values are guaranteed by design only 2.Active clock edge is programmable. Timing is referenced from active edge 40 50 - % taxcl AUD_XCLK Low Time (AUD_XCLK is Input/Output)1, 2 40 50 - % taxper AUD_XCLK period (Input/Output)1, 2 27 ns taoper AUD_BCK period (Output)1, 2 216 ns tsdm AUD_BCK delay from AUD_XCLK transition - 5 ns tsdm AUD_BCK delay from AUD_XCLK transition - 3 ns tlrds AUD_LRCK delay from AUD_BCK transition - 3 ns Table 7: Audio Output Interface Characteristics Figure 10. Audio Output Timing AUD_BCK(Output) AUD_XCLK(Input/Output) t sdm t axch AUD_BCK(Output) AUD_DO[3:0] (Output) AUD_LRCK(Output) t lrds t adsm t axcl t axper t aoperl |
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