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CDC5806 Datasheet(PDF) 4 Page - Texas Instruments

Part No. CDC5806
Description  THREE PLLs BASED CLOCK GENERATOR FOR DIGITAL TV APPLICATIONS
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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CDC5806 Datasheet(HTML) 4 Page - Texas Instruments

   
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ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
TIMING REQUIREMENTS
CDC5806
SCAS760A – MARCH 2004 – REVISED JULY 2004
over operating free-air temperature (unless otherwise noted)(1)
Supply voltage range, VDD
0.5 V to 4.6 V
Input voltage range, VI
(2)
0.5 V to VDD + 0.5 V
Output voltage range, VO
(2)
0.5 V to VDD + 0.5 V
Input current (VI < 0, VI>VDD)
±20 mA
Continuous output current, IO
±50 mA
Package thermal impedance,
Θ
JA
(3): TSSOP20 package
104 C/W
Storage temperature range Tstg
65
°C to 150°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3)
The package thermal impedance is calculated in accordance with JESD 51 (no airflow condition) and JEDEC2S1P (high-k board).
MIN
NOM
MAX
UNIT
VDD
Supply voltage
3
3.3
3.6
V
TA
Operating free-air temperature
-40
85
°C
VIL
Low-level input voltage REF_IN
0.3 VDD
V
VI thresh
Input voltage threshold REF_IN
0.5 VDD
V
VIH
High-level input voltage REF_IN
0.7 VDD
V
VIL(L)
Three level input low for control inputs
0.13 VDD
V
VIM(M)
Three level input mid for control inputs
0.4 VDD
0.6 VDD
V
VIH(H)
Three level input high for control inputs
0.87 VDD
V
IOH
High-level output current LVCMOS
-8
mA
IOL
Low-level output current LVCMOS
8
mA
VI
Input voltage range LVCMOS
0
3.6
V
CL
Output load LVCMOS
5
10
pF
over recommended ranges of supply voltage, load, and operating free-air temperature
PARAMETER
MIN NOM
MAX
UNIT
REF_IN REQUIREMENTS
fCLK_IN
LVCMOS REF_IN clock input frequency
54
MHz
tr / tf
Rise and fall time REF_IN signal (20% to 80%)
4
ns
dutyREF Duty cycle of REF_IN (VDD/2)
40%
60%
AUDSEL, VIDSEL, MCSEL REQUIREMENTS
tr / tf
Rise and fall time (20% to 80%)
4
ns
t1
Transitional time between AUDSEL and VIDSEL control pins(1)
6
ns
(1)
If VIDSEL and AUDSEL are switched from from one state to another state at the same time, then the CPUCLK, ASICCLK, USBCLK, or
MCCLK are affected. This is due to the selected reserved mode with VIDSEL = M and AUDSEL = M. This mode causes the PLL3 to be
bypassed and the REFCLK will be seen with the appropriate divider ratios at the correspondent outputs.
4


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