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LX128C-5F208C Datasheet(PDF) 5 Page - Lattice Semiconductor |
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LX128C-5F208C Datasheet(HTML) 5 Page - Lattice Semiconductor |
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5 / 75 page  Lattice Semiconductor ispGDX2 Family Data Sheet 2 Figure 1. ispGDX2 Block Diagram (256-I/O Device) Introduction The ispGDX2™ family is Lattice’s second generation in-system programmable generic digital crosspoint switch for high speed bus switching and interface applications. The ispGDX2 family is available in two options. The standard device supports sysHSI capability for ultra fast serial communications while the lower-cost “E-series” supports the same high-performance FPGA fabric without the sysHSI Block. This family of switches combines a flexible switching architecture with advanced sysIO interfaces including high performance sysHSI Blocks, and sysCLOCK PLLs to meet the needs of the today’s high-speed systems. Through a muliplexer-intensive architecture, the ispGDX2 facilitates a variety of common switching functions. The availability of on-chip control logic further enhances the power of these devices. A high-performance solution, the family supports bandwidth up to 38Gbps. Every device in the family has a number of PLLs to provide the system designer with the ability to generate multiple clocks and manage clock skews in their systems. GDX Block sysCLOCK PLL sysCLOCK PLL SERDES sysIO Bank sysIO Bank sysIO Bank sysIO Bank SERDES GDX Block SERDES GDX Block SERDES SERDES SERDES SERDES SERDES GDX Block GDX Block GDX Block GDX Block GDX Block FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO ISP & Boundary Scan Test Port sysHSI Block sysHSI Block sysHSI Block sysHSI Block sysCLOCK PLL sysCLOCK PLL Global Routing Pool (GRP) |
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