ADS8402

SLAS154B – DECEMBER 2002 – REVISED MAY 2003

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Table 1. Ideal Input Voltages and Output Codes

DESCRIPTION

ANALOG VALUE

DIGITAL OUTPUT TWOS COMPLEMENT

FULL SCALE RANGE

2Vref

DIGITAL OUTPUT TWOS COMPLEMENT

Least significant bit (LSB)

2Vref/65536

BINARY CODE

HEX CODE

Full scale

Vref

0111 1111 1111 1111

7FFF

Midscale

0

0000 0000 0000 0000

0000

Zero

–Vref

1000 0000 0000 0000

8000

The output data is a full 16-bit word (D15–D0) on DB15–DB0 pins (MSB–LSB) if BYTE is low.

The result may also be read on an 8-bit bus for convenience. This is done by using only pins DB15–DB8. In this case

two reads are necessary: the first as before, leaving BYTE low and reading the 8 most significant bits on pins

DB15–DB8, then bringing BYTE high. When BYTE is high, the low bits (D7–D0) appears on pins DB15–D8.

These multiword read operations can be done with multiple active RD (toggling) or with RD tied low for simplicity.

BYTE

DATA READ OUT

BYTE

DB15–DB8

DB7–DB0

High

D7–D0

All one’s

Low

D15–D8

D7–D0

RESET

RESET is an asynchronous active low input signal (that works independantly of CS). Minimum RESET low time is

20 ns. Current conversion will be aborted no later than 50 ns after the converter is in the reset mode. In addition, all

output latches are cleared (set to zero’s) after RESET. The converter goes back to normal operation mode no later

than 20 ns after RESET input is brought high.

The converter starts the first sampling period 20 ns after the rising edge of RESET. Any sampling period except for

the one immediately after a RESET is started with the falling edge of the previous BUSY signal or the falling edge

of CS, whichever is later.

POWER-ON INITIALIZATION

One RESET pulse followed by three conversion cycles must be given to the converter after powerup to ensure proper

operation. The next pulse can be issued once both +VA and +VBD reach 95% of the minimum required value.

LAYOUT

For optimum performance, care should be taken with the physical layout of the ADS8402 circuitry.

As the ADS8402 offers single-supply operation, it is often used in close proximity with digital logic, microcontrollers,

microprocessors, and digital signal processors. The more digital logic present in the design and the higher the

switching speed, the more difficult it is to achieve good performance from the converter.

The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground

connections and digital inputs that occur just prior to latching the output of the analog comparator. Thus, driving any

single conversion for an n-bit SAR converter, there are at least n windows in which large external transient voltages

can affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic,

or high power devices.

The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external

event.

On average, the ADS8402 draws very little current from an external reference, as the reference voltage is internally

buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive the bypass

capacitor or capacitors without oscillation. A 0.1-

µF bypass capacitor and 1-µF storage capacitor are recommended

from pin 1 (REFIN) directly to pin 48 (REFM). REFM and AGND should be shorted on the same ground plane under

the device.