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CR16MCS9VJE24 Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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CR16MCS9VJE24 Datasheet(HTML) 1 Page - National Semiconductor (TI) |
1 / 156 page ©2001 National Semiconductor Corporation www.national.com Interrupt Control January 2002 CR16HCS5/CR16HCS9/CR16MAR5/CR16MAS5 CR16MAS9/CR16MBR5/CR16MCS5/CR16MCS9 Family of 16-bit CAN-enabled CompactRISC Microcontrollers 1.0 General Description The family of 16-bit CompactRISC™ microcontroller is based on a Reduced Instruction Set Computer (RISC) ar- chitecture. The device operates as a complete microcom- puter with all system timing, interrupt logic, flash program memory or ROM memory, RAM, EEPROM data memory, and I/O ports included on-chip. It is ideally suited to a wide range of embedded controller applications because of its high performance, on-chip integrated features and low power consumption resulting in decreased system cost. The device offers the high performance of a RISC architec- ture while retaining the advantages of a traditional Com- plex Instruction Set Computer (CISC): compact code, on- chip memory and I/O, and reduced cost. The CPU uses a three-stage instruction pipeline that allows execution of up to one instruction per clock cycle, or up to 25 million in- structions per second (MIPS) at a clock rate of 24 MHz. The device contains a FullCAN class, CAN serial interface for low/high speed applications with 15 orthogonal mes- sage buffers, each supporting standard as well as extend- ed message identifiers. TRI-STATE® is a registered trademark of National Semiconductor Corporation. 64k-Byte Flash Program Memory CR16CAN Core Bus Peripheral Bus Clock Generator Slow Clk* Processing Unit I/O µWire/SPI 12-ch Fast Clk 3k-Byte Peripheral Bus Controller Power-on-Reset 2176-Byte RAM EEPROM Data MIWU 2 Analog Comparators Timing and Watchdog Power Manage- ment 2x MFT 2x USART CR16B RISC Core 8-bit A/D ACCESS bus 4x VTU Memory Memory FullCAN 2.0B 1.5k-Byte ISP Please note that not all family members contain same peripheral modules and features. Block Diagram |
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