Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

XRD6414 Datasheet(PDF) 5 Page - Exar Corporation

Part No. XRD6414
Description  CMOS 10-Bit, 20 MSPS, High Speed Analog-to-Digital Converter with 4:1 Input Analog Multiplexer
Download  16 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  EXAR [Exar Corporation]
Homepage  http://www.exar.com
Logo 

XRD6414 Datasheet(HTML) 5 Page - Exar Corporation

 
Zoom Inzoom in Zoom Outzoom out
 5 / 16 page
background image
XRD6414
5
Rev. 1.00
ELECTRICAL CHARACTERISTICS (CONT’D)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
Digital Inputs
VIH
Digital Input High Voltage
3.5
V
VIL
Digital Input Low Voltage
1.5
V
IIN
DC Leakage Currents6
CLK, OE, PD, A0, A1
5
mA
Between AGND and AVDD
Input Capacitance
5
pF
Digital Outputs
VOH
Output High Voltage
4.5
V
VOL
Output Low Voltage
0.4
V
IOZ
High-Z Leakage
–10
10
mA
OE = high, or PD = high
tDL
Data Valid Delay2
10
12
14
ns
tDEN
Data Enable Delay
10
12
14
ns
tDHZ
Data High-Z Delay
7
8
9
ns
Pipeline Delay (Latency)
3
cycles
Time delay between CLK and data
output
Power Supplies
IDD(PD)
Power Down (IDD)
0.3
0.5
mA
PD = high, excluding current
through reference ladder
AVDD
Operating Voltage7,8
4.5
5.0
5.5
V
DVDD
Logic Power Supply9
2.7
5.5
V
IDD
Supply Current (IDD)
24
32
mA
PD = low
Notes
1 Tester measures code transitions by dithering the voltage of the analog input (VIN). The difference between the measured and the
ideal code width (VREF/1024) is the DNL error. The INL error is the maximum distance (in LSBs) from the best fit line to
any transition voltage. Accuracy is a function of the sampling rate (FS).
2 Specified values guarantee functionality. Refer to other parameters for accuracy.
3 Guaranteed. Not tested.
4 –1 dB bandwidth is a measure of performance of the A/D input stage (S/H + amplifier). Refer to other parameters for accuracy
within the specified bandwidth.
5 See VIN equivalent circuit. Switched capacitor analog input requires driver with low output resistance.
6 All inputs have diodes to AVDD and AGND. Input DC currents will not exceed specified limits for any input voltage between AGND
and AVDD.
7 The GND pins are connected through the silicon substrate. Connect all GND pins together at the package and to the analog
ground plane. DGND and GND are connected through junction diodes. See logic output interface section.
8 The VDD pins should be tied together at the package.
9 See logic output interface section.
Specifications are subject to change without notice


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn