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SN74ALS155 Datasheet(PDF) 1 Page - Texas Instruments

Part No. SN74ALS155
Description  DUAL 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
Logo TI - Texas Instruments

SN74ALS155 Datasheet(HTML) 1 Page - Texas Instruments

  SN74ALS155 Datasheet HTML 1Page - Texas Instruments SN74ALS155 Datasheet HTML 2Page - Texas Instruments SN74ALS155 Datasheet HTML 3Page - Texas Instruments SN74ALS155 Datasheet HTML 4Page - Texas Instruments  
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SN74ALS155
DUAL 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER
SDAS140 — NOVEMBER 1987
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
© 1987, Texas Instruments Incorporated
1
PRODUCTION DATA information is current as of
publication date. Products conform to specifications
per the terms of Texas Instruments standard
warranty.
Production
processing
does
not
necessarily include testing of all parameters.
Applications:
Dual 2-Line to 4-Line Decoder
Dual 1-Line to 4-Line Demultiplexer
3-Line to 8-Line Decoder
1-Line to 8-Line Demultiplexer
Individual Strobes Simplify Cascading For
Decoding or Demultiplexing Larger Words
Package Options Include Plastic “Small
Outline” Packages and Standard Plastic
300-mil DIPs
description
The
′ALS155 circuits feature dual 1-line to 4-line
demultiplexers
with
individual
strobes
and
common binary-address inputs in a single 16-pin
package. When both sections are enabled, the
common
binary-address
inputs
sequentially
select and route associated input data to the
appropriate output of each section. The individual
strobes permit enabling or disabling each of the
4-bit sections as desired.
Data applied to input 1C is inverted at its outputs
and data applied at input 2C is not inverted
through its outputs. The inverter following the 1C
data input permits use of the
′ALS155 as a 3-line
to 8-line demultiplexer without external gating. All
inputs
are
clamped
with
high-performance
Schottky diodes to suppress line ringing and
simplify system design.
The SN74ALS155 is characterized for operation
from 0
°C to 70°C.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1C
1G
B
1Y3
1Y2
1Y1
1Y0
GND
VCC
2C
2G
A
2Y3
2Y2
2Y1
2Y0
D or N Package
(Top View)
logic diagram (positive logic)
OUTPUT
1Y0
7
OUTPUT
1Y1
6
5 OUTPUT
1Y2
4 OUTPUT
1Y3
9 OUTPUT
2Y0
10 OUTPUT
2Y1
11 OUTPUT
2Y2
12 OUTPUT
2Y3
STROBE
1G
2
DATA
1C
1
SELECT
B
3
SELECT
A
13
DATA
2C
15
STROBE
1G
14


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