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SAA4998H Datasheet(PDF) 31 Page - NXP Semiconductors |
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SAA4998H Datasheet(HTML) 31 Page - NXP Semiconductors |
31 / 39 page 2004 Feb 18 31 Philips Semiconductors Product specification Field and line rate converter with noise reduction and embedded memory SAA4998H Notes 1. All inputs except inputs with internal pull-up or pull-down resistor. These inputs have an absolute leakage current of maximum 50 µA. 2. Timing characteristics are measured with CL =15pF. 3. All inputs except SNERT interface inputs, CLK32 input and BST/TEST inputs. BST interface; see Fig.6 Tcy(BST) BST cycle time − 1 −µs tsu(i)(BST) input set-up time 3 −− ns th(i)(BST) input hold time 6 −− ns th(o)(BST) output hold time 4 −− ns td(o)(BST) output delay −− 30 ns SNERT interface; see Fig.7 tSNRST(H) SNRST pulse HIGH time 500 −− ns td(SNRST-SNCL) delay SNRST pulse to SNCL LOW time 200 −− ns Tcy(SNCL) SNCL cycle time 0.5 − 1 µs tsu(i)(SNCL) input set-up time to SNCL 53 −− ns th(i)(SNCL) input hold time to SNCL 10 −− ns th(o) output hold time 30 −− ns td(o) output delay −− 330 ns to(en) output enable time 210 −− ns SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT stable power supply RST coc003 CLK32 ≥10 cycles of CLK32 Fig.4 Timing for RST input. |
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