SAA4998H datasheet(7/39 Pages) PHILIPS

Part #	SAA4998H

Description	Field and line rate converter with noise reduction and embedded memory

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Manufacturer	PHILIPS [NXP Semiconductors]

Direct Link	http://www.nxp.com

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7 / 39 page

2004 Feb 18

7

Philips Semiconductors

Product speciﬁcation

Field and line rate converter with noise

reduction and embedded memory

SAA4998H

6

PINNING

SYMBOL

TYPE

DESCRIPTION(1)(2)(3)

YG5/DPIP5

1

output/input

PIP mode disabled: bus G luminance output bit 5;

PIP mode enabled: PIP data input bit 5

YG4/DPIP4

2

output/input

PIP mode disabled: bus G luminance output bit 4;

PIP mode enabled: PIP data input bit 4

VDDE

3

supply

supply voltage of output pads (3.3 V)

VSSE

4

ground

ground of output pads

YG3/DPIP3

5

output/input

PIP mode disabled: bus G luminance output bit 3;

PIP mode enabled: PIP data input bit 3

YG2/DPIP2

6

output/input

PIP mode disabled: bus G luminance output bit 2;

PIP mode enabled: PIP data input bit 2

YG1/DPIP1

7

output/input

PIP mode disabled: bus G luminance output bit 1;

PIP mode enabled: PIP data input bit 1

YG0/DPIP0

8

output/input

PIP mode disabled: bus G luminance output bit 0 (LSB);

PIP mode enabled: PIP data input bit 0 (LSB)

UVG7/QPIP7

9

output

PIP mode disabled: bus G chrominance output bit 7 (MSB);

PIP mode enabled: PIP data output bit 7 (MSB)

UVG6/QPIP6

10

output

PIP mode disabled: bus G chrominance output bit 6;

PIP mode enabled: PIP data output bit 6

UVG5/QPIP5

11

output

PIP mode disabled: bus G chrominance output bit 5;

PIP mode enabled: PIP data output bit 5

UVG4/QPIP4

12

output

PIP mode disabled: bus G chrominance output bit 4;

PIP mode enabled: PIP data output bit 4

UVG3/QPIP3

13

output

PIP mode disabled: bus G chrominance output bit 3;

PIP mode enabled: PIP data output bit 3

n.c./LLC

14

input

PIP mode disabled: not connected;

PIP mode enabled: line locked clock signal for PIP mode

VSSE

15

ground

ground of output pads

n.c./SWCK2

16

input

PIP mode disabled: not connected;

PIP mode enabled: serial write clock for PIP memory

UVG2/QPIP2

17

output

PIP mode disabled: bus G chrominance output bit 2;

PIP mode enabled: PIP data output bit 2

UVG1/QPIP1

18

output

PIP mode disabled: bus G chrominance output bit 1;

PIP mode enabled: PIP data output bit 1

UVG0/QPIP0

19

output

PIP mode disabled: bus G chrominance output bit 0 (LSB);

PIP mode enabled: PIP data output bit 0 (LSB)

n.c./RSTW2

20

input

PIP mode disabled: not connected;

PIP mode enabled: write reset clock for PIP memory

n.c./OIE2

21

input

PIP mode disabled: not connected;

PIP mode enabled: output enable for PIP memory output QPIPx

n.c./IE2

22

input

PIP mode disabled: not connected;

PIP mode enabled: input enable for PIP memory

VDDP

23

supply

high supply voltage of the internal ﬁeld memories (3.3 V)

n.c./WE2

24

input

PIP mode disabled: not connected;

PIP mode enabled: write enable for PIP memory

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