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S4242 Datasheet(PDF) 2 Page - Summit Microelectronics, Inc.

Part No. S4242
Description  Dual Voltage Supervisory Circuit With Watchdog Timer
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Maker  SUMMIT [Summit Microelectronics, Inc.]
Homepage  http://www.summitmicro.com
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 2 page
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2
S4242/S42WD42/S4261/S42WD61
2025 6.0 4/17/00
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias
............................................................................................................................... -40°C to +85°C
Storage Temperature
..................................................................................................................................... -65°C to +125°C
Soldering Temperature (less than 10 seconds) ................................................................................................................... 300°C
Supply Voltage
............................................................................................................................................................. 0 to 6.5V
Voltage on Any Pin
....................................................................................................................................... -0.3V to VCC+0.3V
ESD Voltage (JEDEC method) .......................................................................................................................................... 2,000V
NOTE: These are STRESS ratings only. Appropriate conditions for operating these devices are given elsewhere in this specification. Stresses
beyond those listed here may permanently damage the part. Prolonged exposure to maximum ratings may affect device reliability.
2.7V to 4.5V
4.5V to 5.5V
Symbol
Parameter
Conditions
Min
Max
Min
Max
Units
fSCL
SCL Clock Frequency
0
100
400
KHz
tLOW
Clock Low Period
4.7
1.3
µs
tHIGH
Clock High Period
4.0
0.6
µs
tBUF
Bus Free Time
Before New Transmission
4.7
1.3
µs
tSU:STA
Start Condition Setup Time
4.7
0.6
µs
tHD:STA
Start Condition Hold Time
4.0
0.6
µs
tSU:STO
Stop Condition Setup Time
4.7
0.6
µs
tAA
Clock to Output
SCL Low to SDA Data Out Valid
0.3
3.5
0.2
0.9
µs
tDH
Data Out Hold Time
SCL Low to SDA Data Out Change
0.3
0.2
µs
tR
SCL and SDA Rise Time
1000
300
ns
tF
SCL and SDA Fall Time
300
300
ns
tSU:DAT
Data In Setup Time
250
100
ns
tHD:DAT
Data In Hold Time
0
0
ns
TI
Noise Spike Width
Noise Suppression Time Constant
100
100
ns
@ SCL, SDA Inputs
tWR
Write Cycle Time
10
10
ms
AC ELECTRICAL CHARACTERISTICS
(over recommended operating conditions unless otherwise specified)
2025 PGM T3.0
2025 PGM T2.0
DC ELECTRICAL CHARACTERISTICS (over recommended operating conditions unless otherwise specified)
Symbol
Parameter
Conditions
Min
Max
Units
SCL = CMOS Levels @ 100KHz
VCC =5.5V
3
mA
ICC
Supply Current (CMOS)
SDA = Open
All other inputs = GND or VCC
VCC =3.3V
2
mA
ISB
Standby Current (CMOS)
SCL = SDA = VCC
VCC =5.5V
50
µA
All other inputs = GND
ILI
Input Leakage
VIN = 0 To VCC
10
µA
ILO
Output Leakage
VOUT = 0 To VCC
10
µA
VIL
Input Low Voltage
SCL, SDA, RESET# (pin 2)
0.3xVCC
V
VIH
Input High Voltage
SCL, SDA, RESET (pin7)
0.7xVCC
V
VOL
Output Low Voltage
IOL = 3mA SDA
0.4
V
VCC =3.3V
25
µA
Temperature
Min
Max
Commercial
0°C
+70°C
Industrial
-40°C
+85°C
RECOMMENDED OPERATING CONDITIONS
2025 PGM T1.0




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