MSP430F11x

MIXED SIGNAL MICROCONTROLLER

SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004

14

POST OFFICE BOX 655303

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

Schmitt-trigger inputs Port 1 to Port P2; P1.0 to P1.7, P2.0 to P2.5

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VIT+

Positive-going input threshold voltage

VCC = 2.2 V

1.1

1.3

V

VIT+

Positive-going input threshold voltage

VCC = 3 V

1.5

1.8

V

VIT−

Negative-going input threshold voltage

VCC = 2.2 V

0.4

0.9

V

VIT−

Negative-going input threshold voltage

VCC = 3 V

.90

1.2

V

Vhys

Input voltage hysteresis, (VIT+ − VIT−)

VCC = 2.2 V

0.3

1

V

Vhys

Input voltage hysteresis, (VIT+ − VIT−)

VCC = 3 V

0.5

1.4

V

standard inputs − RST/NMI; TCK, TMS, TDI

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VIL

Low-level input voltage

VCC = 2.2 V / 3 V

VSS

VSS+0.6

V

VIH

High-level input voltage

VCC = 2.2 V / 3 V

0.8

×VCC

VCC

V

inputs Px.x, TAx

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

Port P1, P2: P1.x to P2.x, External trigger signal

2.2 V/3 V

1.5

cycle

t(int)

External interrupt timing

Port P1, P2: P1.x to P2.x, External trigger signal

for the interrupt flag, (see Note 1)

2.2 V

62

ns

t(int)

External interrupt timing

for the interrupt flag, (see Note 1)

3 V

50

ns

2.2 V/3 V

1.5

cycle

t(cap)

Timer_A, capture timing

TA0, TA1, TA2 (see Note 2)

2.2 V

62

ns

t(cap)

Timer_A, capture timing

TA0, TA1, TA2 (see Note 2)

3 V

50

ns

f(TAext)

Timer_A clock frequency

TACLK, INCLK t(H) = t(L)

2.2 V

8

MHz

f(TAext)

Timer_A clock frequency

externally applied to pin

TACLK, INCLK t(H) = t(L)

3 V

10

MHz

f(TAint)

Timer_A clock frequency

SMCLK or ACLK signal selected

2.2 V

8

MHz

f(TAint)

Timer_A clock frequency

SMCLK or ACLK signal selected

3 V

10

MHz

NOTES:

1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with

trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in

MCLK cycles.

2. The external capture signal triggers the capture event every time the mimimum t(cap) cycle and time parameters are met. A capture

may be triggered with capture signals even shorter than t(cap). Both the cycle and timing specifications must be met to ensure a

correct capture of the 16-bit timer value and to ensure the flag is set.

leakage current

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Ilkg(Px.x)

High-impedance leakage current

Port P1: P1.x, 0

≤ ×≤ 7

(see Notes 1 and 2)

VCC = 2.2 V/3 V,

±50

nA

Ilkg(Px.x)

High-impedance leakage current

Port P2: P2.x, 0

≤ ×≤ 5

(see Notes 1 and 2)

VCC = 2.2 V/3 V,

±50

nA

NOTES:

1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.

2. The leakage of the digital port pins is measured individually. The port pin must be selected for input and there must be no optional

pullup or pulldown resistor.