Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

LMF100 Datasheet(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. LMF100
Description  High Performance Dual Switched Capacitor Filter
Download  28 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
Logo NSC - National Semiconductor (TI)

LMF100 Datasheet(HTML) 4 Page - National Semiconductor (TI)

  LMF100 Datasheet HTML 1Page - National Semiconductor (TI) LMF100 Datasheet HTML 2Page - National Semiconductor (TI) LMF100 Datasheet HTML 3Page - National Semiconductor (TI) LMF100 Datasheet HTML 4Page - National Semiconductor (TI) LMF100 Datasheet HTML 5Page - National Semiconductor (TI) LMF100 Datasheet HTML 6Page - National Semiconductor (TI) LMF100 Datasheet HTML 7Page - National Semiconductor (TI) LMF100 Datasheet HTML 8Page - National Semiconductor (TI) LMF100 Datasheet HTML 9Page - National Semiconductor (TI) Next Button
Zoom Inzoom in Zoom Outzoom out
 4 / 28 page
background image
Logic Input Characteristics
Boldface limits apply for T
MIN to TMAX; all other limits TA = TJ = 25˚C.
Parameter
Conditions
LMF100CCN
LMF100CIWM
Units
Typical
Tested
Design
Typical
Tested
Design
(Note 8)
Limit
Limit
(Note 8)
Limit
Limit
(Note 9)
(Note 10)
(Note 9)
(Note 10)
CMOS Clock
MIN Logical “1”
V
+ = +5V, V= −5V,
+3.0
+3.0
+3.0
V
Input Voltage
MAX Logical “0”
VLSh = 0V
−3.0
−3.0
−3.0
V
MIN Logical “1”
V
+ = +10V, V= 0V,
+8.0
+8.0
+8.0
V
MAX Logical “0”
VLSh = +5V
+2.0
+2.0
+2.0
V
TTL Clock
MIN Logical “1”
V
+ = +5V, V= −5V,
+2.0
+2.0
+2.0
V
Input Voltage
MAX Logical “0”
VLSh = 0V
+0.8
+0.8
+0.8
V
MIN Logical “1”
V
+ = +10V, V= 0V,
+2.0
+2.0
+2.0
V
MAX Logical “0”
VLSh = 0V
+0.8
+0.8
+0.8
V
CMOS Clock
MIN Logical “1”
V
+ = +2.5V, V= −2.5V,
+1.5
+1.5
+1.5
V
Input Voltage
MAX Logical “0”
VLSh = 0V
−1.5
−1.5
−1.5
V
MIN Logical “1”
V
+ = +5V, V= 0V,
+4.0
+4.0
+4.0
V
MAX Logical “0”
VLSh = +2.5V
+1.0
+1.0
+1.0
V
TTL Clock
MIN Logical “1”
V
+ = +5V, V= 0V,
+2.0
+2.0
+2.0
V
Input Voltage
MAX Logical “0”
VLSh = 0V, VD
+ = 0V
+0.8
+0.8
+0.8
V
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is in-
tended to be functional. These ratings do not guarantee specific performance limits, however. For guaranteed specifications and test conditions, see the Electrical
Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not op-
erated under the listed test conditions.
Note 2: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V
or V
IN > V
+) the absolute value of current at that pin should be limited
to 5 mA or less. The sum of the currents at all pins that are driven beyond the power supply voltages should not exceed 20 mA.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is PD = (TJMAX −TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device,
TJMAX = 125˚C, and the typical junction-to-ambient thermal resistance of the LMF100CIN when board mounted is 55˚C/W. For the LMF100CIWM this number is
66˚C/W.
Note 4: The accuracy of the Q value is a function of the center frequency (f0). This is illustrated in the curves under the heading “Typical Peformance Characteristics”.
Note 5: Vos1,Vos2, and Vos3 refer to the internal offsets as discussed in the Applications Information section 3.4.
Note 6: Crosstalk between the internal filter sections is measured by applyinga1VRMS 10 kHz signal to one bandpass filter section input and grounding the input
of the other bandpass filter section. The crosstalk is the ratio between the output of the grounded filter section and the 1 VRMS input signal of the other section.
Note 7: The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then shorting that output
to the negative supply. The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage swing and then shorting
that output to the positive supply. These are the worst case conditions.
Note 8: Typicals are at 25˚C and represent most likely parametric norm.
Note 9: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 10: Design limits are guaranteed to National’s AOQL (Average Outgoing Quality Level) but are not 100% tested.
Note 11: Human body model, 100 pF discharged through a 1.5 k
Ω resistor.
Note 12: In 50:1 mode the output noise is 3 dB higher.
Note 13: In 50:1 mode the clock feedthrough is 6 dB higher.
Note 14: A military RETS specification is available upon request.
www.national.com
4


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28 


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn