Table 1 - DLVR Control Logic Detail

Operation Overview (Cont’d)

Figure 2 - DLVR Communication Model

Power/

Speed

Option

Power/Speed

Description

Operating

Mode

Over

Sample

Delay

Between

Samples

Normal

ADC

Cycles

Special

ADC

Cycles

Special

ADC Cycle

Interval

F

Fast

No

No

1 (P)

1 (Z or T)

255

N

Noise Reduced

Yes

No

1 (P)

1 (Z or T)

255

L

Low Power

Yes

Yes

1 (P)

1 (Z or T)

31

No

User Defined

1 (P)

n/a

Never

Sleep (Wake All)

No

User Defined

1 (P)

2 (Z + T)

Always

Note 1) Wake from sleep with pressure only reading is not available with SPI interface (I2C only).

Control Logic

S

Free

Running

Triggered

Free Running Mode [(F)ast, (N)oise Reduced and (L)ow Power Option]

Cycle Type

Internal Operation DSP Delay

ADC (P)

DSP Delay

ADC (P)

DSP Delay

ADC (P)

ADC (T or Z) DSP Delay ADC (P)

New Data Available

Note 1: See Table 1 for frequency of Special Cycles

Normal Cycle

Normal Cycle

Triggered Mode - Wake All [(S)leep Option]

or

SPI (SS)

Read Data

Internal Operation

ADC (Z) ADC (T) ADC (P) DSP

ADC (Z) ADC (T) ADC (P) DSP

Sleep

New Data Available

Wake All

Wake All

Sleep

I2C

Read Data

Sleep

Triggered Mode - Wake Pressure [(S)leep Option]

Internal Operation

ADC (P) DSP

ADC (P) DSP

Sleep

New Data Available

I2C

Wake P.

Read Data

Wake P.

Sleep

Sleep

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