Pinout Description

(See Connection Diagram) (Continued)

Pin 6, V

Pin 7, GROUND Connection: This pin is the ground return,

and is internally connected to the mounting tab.

Pin 8, CURRENT SENSE Output: This pin provides the

sourcing current sensing output signal, which is typically

377 µA/A.

Pin 9, THERMAL FLAG Output: This pin provides the ther-

mal warning flag output signal. Pin 9 becomes active-low at

145˚C (junction temperature). However the chip will not shut

itself down until 170˚C is reached at the junction.

Pin 10, OUTPUT 2: Half H-bridge number 2 output.

Pin 11, BOOTSTRAP 2 Input: Bootstrap capacitor pin for

Half H-bridge number 2. The recommended capacitor

(10 nF) is connected between pins 10 and 11.

TABLE 1. Logic Truth Table

PWM

Dir

Brake

Active Output Drivers

H

H

L

Source 1, Sink 2

H

L

L

Sink 1, Source 2

L

X

L

Source 1, Source 2

H

H

H

Source 1, Source 2

H

L

H

Sink 1, Sink 2

L

X

H

NONE

Application Information

TYPES OF PWM SIGNALS

The LMD18200 readily interfaces with different forms of

PWM signals. Use of the part with two of the more popular

forms of PWM is described in the following paragraphs.

Simple, locked anti-phase PWM consists of a single, vari-

able duty-cycle signal in which is encoded both direction and

amplitude information (see

Figure 2).A50% duty-cycle

PWM signal represents zero drive, since the net value of

voltage (integrated over one period) delivered to the load is

zero. For the LMD18200, the PWM signal drives the direc-

tion input (pin 3) and the PWM input (pin 5) is tied to logic

high.

Sign/magnitude PWM consists of separate direction (sign)

and amplitude (magnitude) signals (see

Figure 3). The (ab-

solute) magnitude signal is duty-cycle modulated, and the

absence of a pulse signal (a continuous logic low level) rep-

resents zero drive. Current delivered to the load is propor-

tional to pulse width. For the LMD18200, the DIRECTION in-

put (pin 3) is driven by the sign signal and the PWM input

(pin 5) is driven by the magnitude signal.

SIGNAL TRANSITION REQUIREMENTS

To ensure proper internal logic performance, it is good prac-

tice to avoid aligning the falling and rising edges of input sig-

nals. A delay of at least 1 µsec should be incorporated be-

tween transitions of the Direction, Brake, and/or PWM input

signals. A conservative approach is be sure there is at least

500ns delay between the end of the first transition and the

beginning of the second transition. See

Figure 4.

DS010568-4

FIGURE 2. Locked Anti-Phase PWM Control

DS010568-5

FIGURE 3. Sign/Magnitude PWM Control

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