CY7C43642
CY7C43662
CY7C43682
Document #: 38-06019 Rev. *B
Page 11 of 30
AC Test Loads and Waveforms (-10 and -15)
AC Test Loads and Waveforms (-7)
3.0V
5V
OUTPUT
R2 = 680
Ω
CL = 30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
≤ 3ns
≤ 3 ns
ALL INPUT PULSES
R1 = 1.1k
Ω
3.0V
GND
90%
10%
90%
10%
≤ 3ns
≤ 3 ns
ALL INPUT PULSES
I/O
50
Ω
VCC/2
Z0 = 50
Ω
Switching Characteristics Over the Operating Range
Parameter
Description
CY7C43642/62/82
-7
CY7C43642/62/82
-10
CY7C43642/62/82
-15
Unit
Min.
Max.
Min.
Max.
Min.
Max.
fS
Clock Frequency, CLKA or CLKB
133
100
67
MHz
tCLK
Clock Cycle Time, CLKA or CLKB
7.5
10
15
ns
tCLKH
Pulse Duration, CLKA or CLKB HIGH
3.5
4
6
ns
tCLKL
Pulse Duration, CLKA or CLKB LOW
3.5
4
6
ns
tDS
Set-up Time, A0–35 before CLKA↑ and B0–35
before CLKB
↑
3
4
5
ns
tENS
Set-up Time, CSA, W/RA, ENA, and MBA before
CLKA
↑; CSB, W/RB, ENB, and MBB before
CLKB
↑
3
4
5
ns
tRSTS
Set-up Time, RST1, RST2, RT1 or RT2 LOW
before CLKA
↑ or CLKB↑[17]
2.5
4
5
ns
tFSS
Set-up Time, FS0 and FS1 before RST1 and
RST2 HIGH
6
7
7.5
ns
tSDS
Set-up Time, FS0 before CLKA
↑
3
4
5
ns
tSENS
Set-up Time, FS1 before CLKA
↑
3
4
5
ns
tFWS
Set-up Time, FWFT before CLKA
↑
0
0
0
ns
tDH
Hold Time, A0–35 after CLKA↑ and B0–35 after
CLKB
↑
0
0
0
ns
tENH
Hold Time, CSA, W/RA, ENA, and MBA after
CLKA
↑; CSB, W/RB, ENB, and MBB after
CLKB
↑
0
0
0
ns
tRSTH
Hold Time, RST1, RST2, RT1 or RT2 LOW after
CLKA
↑ or CLKB↑[17]
1
2
4
ns
tFSH
Hold Time, FS0 and FS1 after RST1 and RST2
HIGH
1
1
2
ns
tSDH
Hold Time, FS0 after CLKA
↑
0
0
0
ns
tSENH
Hold Time, FS1 after CLKA
↑
0
0
0
ns
Note:
17. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between the CLKA cycle and the CLKB
cycle.
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