CYWUSB6932
CYWUSB6934
Document 38-16007 Rev. *G
Page 2 of 30
3.1
Applications Support
The CYWUSB6932/CYWUSB6934 ICs are supported by the
CY3632 WirelessUSB Development Kit. The development kit
provides all of the materials and documents needed to cut the
cord on wired applications including two radio modules that
connect directly to two prototyping platform boards, compre-
hensive WirelessUSB protocol code examples a WirelessUSB
Listener tool and all of the associated schematics, gerber files
and bill of materials.
The CY4632 WirelessUSB LS Keyboard Mouse Reference
Design provides a production-worthy example of a wireless
mouse and keyboard system.
The CY3633 WirelessUSB LS Gaming Development Kit
provides support for designing a wireless gamepad for the
major gaming consoles and is offered as an accessory to the
CY3632 WirelessUSB.
4.0
Functional Overview
The CYWUSB6932/CYWUSB6934 ICs provide a complete
WirelessUSB LS SPI to antenna radio modem. The SoC is
designed to implement wireless devices operating in the
worldwide 2.4-GHz Industrial, Scientific, and Medical (ISM)
frequency band (2.400 GHz–2.4835 GHz). It is intended for
systems compliant with world-wide regulations covered by
ETSI EN 301 489-1 V1.4.1, ETSI EN 300 328-1 V1.3.1
(European Countries); FCC CFR 47 Part 15 (USA and
Industry Canada) and ARIB STD-T66 (Japan).
The CYWUSB6934 IC contains a 2.4-GHz radio transceiver, a
GFSK modem and a dual DSSS reconfigurable baseband.
The CYWUSB6932 IC contains a 2.4-GHz radio transmit-only,
a GFSK modem and a DSSS baseband. The radio and
baseband are both code- and frequency-agile. Forty-nine
spreading codes selected for optimal performance (Gold
codes) are supported across 78 1-MHz channels yielding a
theoretical spectral capacity of 3822 channels. Both ICs
support a range of up to 10 meters or more.
4.1
2.4-GHz Radio
The receiver and transmitter are a single-conversion low-Inter-
mediate Frequency (low-IF) architecture with fully integrated
IF channel matched filters to achieve high performance in the
presence of interference. An integrated Power Amplifier (PA)
provides an output power control range of 30 dB in seven
steps.
Both
the
receiver
and
transmitter
integrated
Voltage
Controlled Oscillator (VCO) and synthesizer have the agility to
cover the complete 2.4-GHz GFSK radio transmitter ISM
band. The synthesizer provides the frequency-hopping local
oscillator for the transmitter and receiver. The VCO loop filter
is also integrated on-chip.
4.2
GFSK Modem
The transmitter uses a DSP-based vector modulator to
convert the 1-MHz chips to an accurate GFSK carrier.
The receiver uses a fully integrated Frequency Modulator (FM)
detector with automatic data slicer to demodulate the GFSK
signal.
4.3
Dual DSSS Baseband
Data is converted to DSSS chips by a digital spreader.
De-spreading is performed by an oversampled correlator. The
DSSS baseband cancels spurious noise and assembles
properly correlated data bytes.
The DSSS baseband has three operating modes: 64 chips/bit
Single Channel, 32 chips/bit Single Channel, and 32 chips/bit
Single Channel Dual Data Rate (DDR).
4.3.1
64 chips/bit Single Channel
The baseband supports a single data stream operating at
15.625 kbits/sec. The advantage of selecting this mode is its
ability to tolerate a noisy environment. This is because the
15.625 kbits/sec data stream utilizes the longest PN Code
resulting in the highest probability for recovering packets over
the air. This mode can also be selected for systems requiring
data transmissions over longer ranges.
4.3.2
32 chips/bit Single Channel
The baseband supports a single data stream operating at
31.25 kbits/sec.
4.3.3
32 chips/bit Single Channel Dual Data Rate (DDR)
The baseband spreads bits in pairs and supports a single data
stream operating at 62.5 kbits/sec.
4.4
Serializer/Deserializer (SERDES)
The CYWUSB6934 IC has a data Serializer/Deserializer
(SERDES), which provides byte-level framing of transmit and
receive data. Bytes for transmission are loaded into the
SERDES and receive bytes are read from the SERDES via the
SPI interface. The SERDES provides double buffering of
transmit and receive data. While one byte is being transmitted
by the radio the next byte can be written to the SERDES data
register insuring there are no breaks in transmitted data.
After a receive byte has been received it is loaded into the
SERDES data register and can be read at any time until the
next byte is received, at which time the old contents of the
SERDES data register will be overwritten. The CYWUSB6932
IC only has a data Serializer.
Table 4-1. Internal PA Output Power Step Table
PA Setting
Typical Output Power (dBm)
70
6–2.4
5–5.6
4–9.7
3–16.4
2–20.8
1–24.8
0–29.0
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