CY28RS400OCT datasheet(5/19 Pages) CYPRESS

Part #	CY28RS400OCT

Description	Clock Generator for ATI RS400 Chipset

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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CY28RS400

Document #: 38-07637 Rev. *B

Page 5 of 19

Control Registers

Byte 0:Control Register 0

Bit

@Pup

Name

Description

7

1

SRC[T/C]5

SRC[T/C]5 Output Enable

0 = Disable (Hi-Z), 1 = Enable

6

1

SRC[T/C]4

SRC[T/C]4 Output Enable

0 = Disable (Hi-Z), 1 = Enable

5

1

SRC[T/C]3

SRC[T/C]3 Output Enable

0 = Disable (Hi-Z), 1 = Enable

4

1

SRC[T/C]2

SRC[T/C]2 Output Enable

0 = Disable (Hi-Z), 1 = Enable

3

1

SRC[T/C]1

SRC[T/C]1 Output Enable

0 = Disable (Hi-Z), 1 = Enable

2

1

SRC [T/C]0

SRC[T/C]0 Output Enable

0 = Disable (Hi-Z), 1 = Enable

1

SRCS[T/C]1

SRCS[T/C]1 Output Enable

0 = Disable (Hi-Z), 1 = Enable

0

1

SRCS[T/C]0

SRCS[T/C]0 Output Enable

0 = Disable (Hi-Z), 1 = Enable

Byte 1: Control Register 1

Bit

@Pup

Name

Description

7

1

REF2

REF2 Output Enable

0 = Disable, 1 = Enable

6

1

REF1

REF1 Output Enable

0 = Disable, 1 = Enable

5

1

REF0

REF0 Output Enable

0 = Disable, 1 = Enable

4

1

PCI0

PCI0 Output Enable

0 = Disable, 1 = Enable

3

1

USB_48

USB_48MHz Output Enable

0 = Disable, 1 = Enable

2

1

CPU[T/C]2

CPU[T/C]2 Output Enable

0 = Disable (Hi-Z), 1 = Enable

1

CPU[T/C]1

CPU[T/C]1 Output Enable

0 = Disable (Hi-Z), 1 = Enable

0

1

CPU[T/C]0

CPU[T/C]0 Output Enable

0 = Disable (Hi-Z), 1 = Enable

Byte 2: Control Register 2

Bit

@Pup

Name

Description

7

1

CPUT/C

SRCT/C

Spread Spectrum Selection

‘0’ = -0.35%

‘1’ = -0.50%

6

1

USB_48

48MHz Output Drive Strength

0 = 1x, 1 = 2x

5

1

PCI

33MHz Output Drive Strength

0 = 1x, 1 = 2x

4

0

Reserved

3

1

Reserved

20

CPU

SRC

CPU/SRC Spread Spectrum Enable

0 = Spread off, 1 = Spread on

1

Reserved

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CY28RS400OCT Datasheet(PDF) 5 Page - Cypress Semiconductor

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