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3.3V 1K/4K/16K x36 x2 Bidirectional
Synchronous FIFO
CY7C43642AV
CY7C43662AV
CY7C43682AV
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-06020 Rev. *C
Revised December 26, 2002
Features
• 3.3V high-speed, low-power, bidirectional, First-In
First-Out (FIFO) memories
• 1K ×36 ×2 (CY7C43642AV)
• 4K x36 x2 (CY7C43662AV)
• 16K x36 x2 (CY7C43682AV)
• 0.25-micron CMOS for optimum speed/power
• High-speed 133-MHz operation (7.5-ns Read/Write
cycle times)
• Low power
—ICC = 60 mA
—ISB = 10 mA
• Fully asynchronous and simultaneous Read and Write
operations permitted
• Mailbox bypass register for each FIFO
• Parallel Programmable Almost Full and Almost Empty
flags
• Retransmit function
• Standard or FWFT user-selectable mode
• 120-pin TQFP package
• Easily expandable in width and depth
Logic Block Diagram
Port A
Control
Logic
Port B
Control
Logic
Mail1
Register
Write
Pointer
Read
Pointer
Status
Flag Logic
Programmable
Flag Offset
Timing
Mode
Status
Flag Logic
Write
Pointer
Read
Pointer
1K/4K/16K
× 36
Dual Ported
Memory
1K/4K/16K
× 36
Dual Ported
Memory
Mail2
Register
FIFO1,
Mail1
Reset
Logic
FIFO2,
Mail2
Reset
Logic
CLKA
CSA
W/RA
ENA
MBA
RT2
MRST1
FFA/IRA
AFA
FS0
FS1
A0–35
EFA/ORA
AEA
MBF2
MRST2
FFB/IRB
AFB
FWFT/STAN
B0–35
CLKB
CSB
W/RB
ENB
MBB
RT1
EFB/ORB
AEB
MBF1
Registers
(FIFO1)
(FIFo2)
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