ADS114S0x datasheet(7/103 Pages) TI1

Part #	ADS114S0x

Description	Low-Power, Low-Noise, Highly Integrated, 6- and 12-Channel, 4-kSPS, 16-Bit, Delta-Sigma ADC with PGA and Voltage Reference

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ADS114S06, ADS114S08

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SBAS815 – FEBRUARY 2017

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7.5 Electrical Characteristics

minimum and maximum specifications apply from TA = –50°C to +125°C; Typical specifications are at TA = 25°C;

all specifications are at AVDD = 2.7 V to 5.25 V, AVSS = 0 V, DVDD = IOVDD = 3.3 V, all gains, internal reference, internal

oscillator, all data rates, and global chop disabled (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ANALOG INPUTS

Absolute input current

PGA bypassed,

AVSS + 0.1 V

≤ V(AINx) ≤ AVDD – 0.1 V

0.5

nA

PGA enabled, all gains,

V(AINx)MIN ≤ V(AINx) ≤ V(AINx)MAX

–2

0.1

2

Absolute input current drift

PGA bypassed,

AVSS + 0.1 V

≤ V(AINx) ≤ AVDD – 0.1 V

2

pA/°C

PGA enabled, all gains,

V(AINx)MIN ≤ V(AINx) ≤ V(AINx)MAX

2

Differential input current

PGA bypassed,

VCM = AVDD / 2, –VREF ≤ VIN ≤ VREF

1

nA/V

PGA enabled, all gains,

VCM = AVDD / 2, –VREF / Gain ≤ VIN ≤ VREF / Gain

–1

0.02

1

nA

Differential input current drift

PGA bypassed,

VCM = AVDD / 2, –VREF ≤ VIN ≤ VREF

3

pA/°C

PGA enabled, all gains,

VCM = AVDD / 2, –VREF / Gain ≤ VIN ≤ VREF / Gain

1

PGA

Gain settings

1, 2, 4, 8, 16,

32, 64, 128

Startup time

Enabling the PGA in conversion mode

190

µs

SYSTEM PERFORMANCE

Resolution (no missing codes)

16

Bits

DR

Data rate

2.5, 5, 10, 16.6,

20, 50, 60, 100,

200, 400, 800,

1000, 2000, 4000

SPS

INL

Integral nonlinearity (best fit)

PGA bypassed, VCM = AVDD / 2

1

10

ppmFSR

PGA enabled, gain = 1 to 8, VCM = AVDD / 2

2

15

PGA enabled, gain = 16 to 128, VCM = AVDD / 2,

TA = –40°C to +85°C

3

15

VIO

Input offset voltage

TA = 25°C, PGA bypassed

–120

20

120

µV

TA = 25°C, PGA enabled, gain = 1 to 8

–120 / Gain

20 / Gain

120 / Gain

TA = 25°C, PGA enabled, gain = 16 to 128

–15

2

15

TA = 25°C, PGA bypassed, after internal offset

calibration

On the order of noisePP at the

set DR and gain

TA = 25°C, PGA enabled, gain = 1 to 128, after

internal offset calibration

On the order of noisePP at the

set DR and gain

TA = 25°C, PGA bypassed, global chop enabled

–2

0.2

2

TA = 25°C, PGA enabled, gain = 1 to 128,

global chop enabled

–2

0.2

2

Offset drift

TA = –40°C to +85°C, PGA bypassed

–75

10

75

nV/°C

TA = –40°C to +85°C, PGA enabled, gain = 1 to 128

–100

15

100

PGA bypassed

–75

10

75

PGA enabled, gain = 1 to 8

–200

15

200

PGA enabled, gain = 16 to 128

–150

15

150

PGA bypassed, global chop enabled

–10

2

10

PGA enabled, gain = 1 to 128, global chop enabled

–10

2

10

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